| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-bitfield-encoding.s | 10 sbfm w1, w2, #1, #15
11 sbfm x1, x2, #1, #15
|
| D | basic-a64-diagnostics.s | 770 sbfm x3, w13, #0, #0
771 sbfm w12, x9, #0, #0
772 sbfm sp, x3, #3, #5
773 sbfm w3, wsp, #1, #9
774 sbfm x9, x5, #-1, #0
775 sbfm x9, x5, #0, #-1
795 sbfm w3, w5, #32, #1
796 sbfm w7, w11, #19, #32
797 sbfm x29, x30, #64, #0
798 sbfm x10, x20, #63, #64
|
| D | basic-a64-instructions.s | 956 sbfm x1, x2, #3, #4
957 sbfm x3, x4, #63, #63
958 sbfm wzr, wzr, #31, #31
959 sbfm w12, w9, #0, #0
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-bitfield-encoding.s | 10 sbfm w1, w2, #1, #15
11 sbfm x1, x2, #1, #15
|
| D | basic-a64-diagnostics.s | 756 sbfm x3, w13, #0, #0
757 sbfm w12, x9, #0, #0
758 sbfm sp, x3, #3, #5
759 sbfm w3, wsp, #1, #9
760 sbfm x9, x5, #-1, #0
761 sbfm x9, x5, #0, #-1
781 sbfm w3, w5, #32, #1
782 sbfm w7, w11, #19, #32
783 sbfm x29, x30, #64, #0
784 sbfm x10, x20, #63, #64
|
| D | basic-a64-instructions.s | 956 sbfm x1, x2, #3, #4
957 sbfm x3, x4, #63, #63
958 sbfm wzr, wzr, #31, #31
959 sbfm w12, w9, #0, #0
|
| /external/vixl/doc/ |
| D | changelog.md | 39 + MacroAssembler support for `bfm`, `ubfm` and `sbfm`.
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 744 void sbfm(const Register& rd,
790 sbfm(rd, rn, shift, rd.GetSizeInBits() - 1); in asr()
800 sbfm(rd, in sbfiz()
813 sbfm(rd, rn, lsb, lsb + width - 1); in sbfx()
817 void sxtb(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 7); } in sxtb()
820 void sxth(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 15); } in sxth()
823 void sxtw(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 31); } in sxtw()
|
| D | assembler-aarch64.cc | 690 void Assembler::sbfm(const Register& rd, in sbfm() function in vixl::aarch64::Assembler
5600 sbfm(rd, rn_, non_shift_bits, high_bit); in EmitExtendShift()
|
| D | macro-assembler-aarch64.h | 2295 sbfm(rd, rn, immr, imms); in Sbfm()
|
| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 4909 { /* AArch64_SBFMWri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */
4913 { /* AArch64_SBFMXri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */
|
| /external/vixl/test/aarch64/ |
| D | test-cpu-features-aarch64.cc | 423 TEST_NONE(sbfm_0, sbfm(w0, w1, 9, 11))
424 TEST_NONE(sbfm_1, sbfm(x0, x1, 22, 22))
|
| D | test-assembler-aarch64.cc | 6416 TEST(sbfm) { in TEST() argument
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2315 void sbfm(const Register& rd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1005 defm SBFM : BitfieldImm<0b00, "sbfm">;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1851 defm SBFM : BitfieldImm<0b00, "sbfm">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1688 defm SBFM : BitfieldImm<0b00, "sbfm">;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12558 "t\002sb\003sbc\005sbclb\005sbclt\004sbcs\004sbfm\005scvtf\004sdiv\005sd"
17183 …{ 4105 /* sbfm */, AArch64::SBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3, AMFBS_None, …
17184 …{ 4105 /* sbfm */, AArch64::SBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3, AMFBS_None, …
24556 …{ 4105 /* sbfm */, AArch64::SBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3, AMFBS_None, …
24557 …{ 4105 /* sbfm */, AArch64::SBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3, AMFBS_None, …
|