| /external/llvm-project/llvm/test/MC/AArch64/SVE/ |
| D | sdivr-diagnostics.s | 7 sdivr z0.b, p7/m, z0.b, z1.b label
12 sdivr z0.h, p7/m, z0.h, z1.h label
21 sdivr z0.s, p7/m, z1.s, z2.s label
30 sdivr z0.s, p8/m, z0.s, z1.s label
|
| D | sdivr.s | 10 sdivr z0.s, p7/m, z0.s, z31.s label
16 sdivr z0.d, p7/m, z0.d, z31.d label
32 sdivr z0.d, p7/m, z0.d, z31.d label
44 sdivr z0.d, p7/m, z0.d, z31.d label
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-int-div-pred.ll | 49 ; CHECK: sdivr z0.s, p0/m, z0.s, z1.s
51 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg,
59 ; CHECK: sdivr z0.d, p0/m, z0.d, z1.d
61 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %pg,
91 declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>…
92 declare <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>…
|
| D | sve-fixed-length-int-div.ll | 39 ; CHECK-NEXT: sdivr [[RES_HI_HI:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
41 ; CHECK-NEXT: sdivr [[RES_HI_LO:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
66 ; CHECK-NEXT: sdivr [[RES_HI_HI:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
68 ; CHECK-NEXT: sdivr [[RES_HI_LO:z[0-9]+]].s, [[PG]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
96 ; CHECK-NEXT: sdivr [[RES_HI_HI:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
98 ; CHECK-NEXT: sdivr [[RES_HI_LO:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
130 ; VBITS_GE_512-NEXT: sdivr [[RES_HI_HI:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
132 ; VBITS_GE_512-NEXT: sdivr [[RES_HI_LO:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
164 ; VBITS_GE_1024-NEXT: sdivr [[RES_HI_HI:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_HI]].s, [[OP1_HI_HI]].s
166 ; VBITS_GE_1024-NEXT: sdivr [[RES_HI_LO:z[0-9]+]].s, [[PG1]]/m, [[OP2_HI_LO]].s, [[OP1_HI_LO]].s
[all …]
|
| D | llvm-ir-to-intrinsic.ll | 20 ; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
22 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
44 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
122 ; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s
124 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
129 ; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
146 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 212 __ sdivr(z19.VnS(), p1.Merging(), z19.VnS(), z19.VnS()); in TEST() local
767 __ sdivr(z19.VnD(), p3.Merging(), z19.VnD(), z24.VnD()); in TEST() local
1465 __ sdivr(z13.VnS(), p7.Merging(), z13.VnS(), z2.VnS()); in TEST() local
|
| D | test-disasm-sve-aarch64.cc | 2209 COMPARE_PREFIX(sdivr(z20.VnS(), p5.Merging(), z20.VnS(), z23.VnS()), in TEST()
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 1037 &Assembler::sdivr)); in Sdiv()
|
| D | assembler-aarch64.h | 5204 void sdivr(const ZRegister& zd,
|
| D | assembler-sve-aarch64.cc | 2443 void Assembler::sdivr(const ZRegister& zd, in sdivr() function in vixl::aarch64::Assembler
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 148 defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", int_aarch64_sve_sdivr>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 351 …defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", "SDIVR_ZPZZ", int_aarch64_sve_sdivr,…
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 17224 …{ 4121 /* sdivr */, AArch64::SDIVR_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
17225 …{ 4121 /* sdivr */, AArch64::SDIVR_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
24597 …{ 4121 /* sdivr */, AArch64::SDIVR_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
24598 …{ 4121 /* sdivr */, AArch64::SDIVR_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
36187 { 4121 /* sdivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
36188 { 4121 /* sdivr */, 49 /* 0, 4, 5 */, MCK_SVEVectorSReg, AMFBS_HasSVE },
36189 { 4121 /* sdivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
36190 { 4121 /* sdivr */, 49 /* 0, 4, 5 */, MCK_SVEVectorSReg, AMFBS_HasSVE },
36191 { 4121 /* sdivr */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
36192 { 4121 /* sdivr */, 49 /* 0, 4, 5 */, MCK_SVEVectorDReg, AMFBS_HasSVE },
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 714 "llvm.aarch64.sve.sdivr",
10847 1, // llvm.aarch64.sve.sdivr
|