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Searched refs:sel (Results 1 – 25 of 889) sorted by relevance

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/external/libnl/lib/xfrm/
Dselector.c53 static void sel_destroy(struct xfrmnl_sel* sel) in sel_destroy() argument
55 if (!sel) in sel_destroy()
58 if (sel->refcnt != 1) in sel_destroy()
64 nl_addr_put (sel->daddr); in sel_destroy()
65 nl_addr_put (sel->saddr); in sel_destroy()
66 free(sel); in sel_destroy()
80 struct xfrmnl_sel* sel; in xfrmnl_sel_alloc() local
82 sel = calloc(1, sizeof(struct xfrmnl_sel)); in xfrmnl_sel_alloc()
83 if (!sel) in xfrmnl_sel_alloc()
86 sel->refcnt = 1; in xfrmnl_sel_alloc()
[all …]
/external/rust/crates/crossbeam-channel/tests/
Dready.rs23 let mut sel = Select::new(); in smoke1() localVariable
24 sel.recv(&r1); in smoke1()
25 sel.recv(&r2); in smoke1()
26 assert_eq!(sel.ready(), 0); in smoke1()
31 let mut sel = Select::new(); in smoke1() localVariable
32 sel.recv(&r1); in smoke1()
33 sel.recv(&r2); in smoke1()
34 assert_eq!(sel.ready(), 1); in smoke1()
48 let mut sel = Select::new(); in smoke2() localVariable
49 sel.recv(&r1); in smoke2()
[all …]
Dselect.rs22 let mut sel = Select::new(); in smoke1() localVariable
23 let oper1 = sel.recv(&r1); in smoke1()
24 let oper2 = sel.recv(&r2); in smoke1()
25 let oper = sel.select(); in smoke1()
34 let mut sel = Select::new(); in smoke1() localVariable
35 let oper1 = sel.recv(&r1); in smoke1()
36 let oper2 = sel.recv(&r2); in smoke1()
37 let oper = sel.select(); in smoke1()
55 let mut sel = Select::new(); in smoke2() localVariable
56 let oper1 = sel.recv(&r1); in smoke2()
[all …]
/external/python/cffi/demo/
Dcffi-cocoa.py66 get, send, sel = objc.objc_getClass, objc.objc_msgSend, objc.sel_registerName variable
69 sel('stringWithCString:encoding:'),
72 send(get('NSAutoreleasePool'), sel('new'))
73 app = send(get('NSApplication'), sel('sharedApplication'))
74 send(app, sel('setActivationPolicy:'), NSApplicationActivationPolicyRegular)
76 menubar = send(send(get('NSMenu'), sel('new')), sel('autorelease'))
77 appMenuItem = send(send(get('NSMenuItem'), sel('new')), sel('autorelease'))
78 send(menubar, sel('addItem:'), appMenuItem)
79 send(app, sel('setMainMenu:'), menubar)
81 appMenu = send(send(get('NSMenu'), sel('new')), sel('autorelease'))
[all …]
/external/tpm2-tss/test/unit/
DTPML-marshal.c27 TPML_PCR_SELECTION sel = {0}; in tpml_marshal_success() local
28 uint8_t buffer[sizeof(hndl) + sizeof(sel)] = { 0 }; in tpml_marshal_success()
45 sel.count = 2; in tpml_marshal_success()
46 sel.pcrSelections[0].hash = TPM2_ALG_SHA1; in tpml_marshal_success()
47 sel.pcrSelections[0].sizeofSelect = 3; in tpml_marshal_success()
48 sel.pcrSelections[0].pcrSelect[0] = 0xaa; in tpml_marshal_success()
49 sel.pcrSelections[0].pcrSelect[1] = 0xbb; in tpml_marshal_success()
50 sel.pcrSelections[0].pcrSelect[2] = 0xcc; in tpml_marshal_success()
51 sel.pcrSelections[1].hash = TPM2_ALG_SHA256; in tpml_marshal_success()
52 sel.pcrSelections[1].sizeofSelect = 2; in tpml_marshal_success()
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dsel.asm1 (+f0.0) sel(8) g47<1>UD g12<4>UD g13<4>UD { align16 1Q };
2 (-f0.0) sel(8) g25<1>.xyUD g13<4>.zwwwUD 0x40000000UD { align16 1Q };
3 (+f0.0.any4h) sel(8) g30<1>UD g13<4>UD g12<4>UD { align16 1Q };
4 (+f0.0.all4h) sel(8) g16<1>UD g8<4>UD g9<4>UD { align16 1Q };
5 (+f0.0) sel(8) g23<1>UD g8<8,8,1>UD g23<8,8,1>UD { align1 1Q };
6 (+f0.0) sel(16) g42<1>UD g76<8,8,1>UD g78<8,8,1>UD { align1 1H };
7 sel.l(8) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1Q };
8 sel.l(16) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1H };
9 sel.ge(8) g3<1>D g2<0,1,0>D -1D { align1 1Q };
10 sel.l(8) g4<1>D g3<8,8,1>D 1D { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dsel.asm1 (+f0.0) sel(8) g40<1>UD g5<4>UD g6<4>UD { align16 1Q };
2 (-f0.0) sel(8) g6<1>UD g13<8,8,1>UD 0x00000000UD { align1 1Q };
3 (-f0.0) sel(16) g7<1>UD g9<8,8,1>UD 0x00000000UD { align1 1H };
4 (+f0.0) sel(8) g2<1>UD g31<8,8,1>UD g34<8,8,1>UD { align1 1Q };
5 (+f0.0) sel(8) m1<1>UD g67<8,8,1>UD 0x3f800000UD { align1 1Q };
6 (+f0.0) sel(16) g2<1>UD g35<8,8,1>UD g41<8,8,1>UD { align1 1H };
7 (+f0.0) sel(16) m1<1>UD g31<8,8,1>UD 0x3f800000UD { align1 1H };
8 (+f0.0.all4h) sel(8) g45<1>UD g23<4>UD g24<4>UD { align16 1Q };
9 sel.ge(8) g64<1>F g5<8,8,1>F 0x0F /* 0F */ { align1 1Q };
10 sel.ge(16) g17<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 1H };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dsel.asm1 (+f0.0) sel(8) g47<1>UD g12<4>UD g13<4>UD { align16 1Q };
2 (-f0.0) sel(8) g25<1>.xyUD g13<4>.zwwwUD 0x40000000UD { align16 1Q };
3 (+f0.0.any4h) sel(8) g30<1>UD g13<4>UD g12<4>UD { align16 1Q };
4 (+f0.0.all4h) sel(8) g16<1>UD g8<4>UD g9<4>UD { align16 1Q };
5 (+f0.0) sel(8) g2<1>UD g31<8,8,1>UD g34<8,8,1>UD { align1 1Q };
6 (+f0.0) sel(8) g124<1>UD g67<8,8,1>UD 0x3f800000UD { align1 1Q };
7 (+f0.0) sel(16) g2<1>UD g35<8,8,1>UD g41<8,8,1>UD { align1 1H };
8 (+f0.0) sel(16) g120<1>UD g27<8,8,1>UD 0x3f800000UD { align1 1H };
9 sel.ge(8) g64<1>F g9<8,8,1>F 0x0F /* 0F */ { align1 1Q };
10 (-f0.0) sel(8) g16<1>UD g20<8,8,1>UD 0x00000000UD { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dsel.asm1 (+f0.0) sel(8) g6<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 };
2 (-f0.0) sel(8) g2<1>UD g2<8,8,1>UD 0x00000000UD { align1 };
3 (+f0.0) sel(16) g10<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
4 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
5 (+f0.0) sel(8) g4<1>.yF g5<4>.xF 0x0F /* 0F */ { align16 };
6 (-f0.0.z) sel(8) g4<1>.zUD g6<4>.xUD 0x00000000UD { align16 };
7 (+f0.0) sel(8) g2<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
8 (+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
9 (+f0.0) sel(8) g2<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 };
10 (+f0.0) sel(8) m3<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 };
[all …]
/external/iproute2/tc/
Df_u32.c119 static int pack_key(struct tc_u32_sel *sel, __u32 key, __u32 mask, in pack_key() argument
123 int hwm = sel->nkeys; in pack_key()
128 if (sel->keys[i].off == off && sel->keys[i].offmask == offmask) { in pack_key()
129 __u32 intersect = mask & sel->keys[i].mask; in pack_key()
131 if ((key ^ sel->keys[i].val) & intersect) in pack_key()
133 sel->keys[i].val |= key; in pack_key()
134 sel->keys[i].mask |= mask; in pack_key()
143 sel->keys[hwm].val = key; in pack_key()
144 sel->keys[hwm].mask = mask; in pack_key()
145 sel->keys[hwm].off = off; in pack_key()
[all …]
Dm_pedit.c62 struct m_pedit_sel *sel, in pedit_parse_nopopt() argument
124 struct tc_pedit_sel *sel = &_sel->sel; in pack_key() local
126 int hwm = sel->nkeys; in pack_key()
136 sel->keys[hwm].val = tkey->val; in pack_key()
137 sel->keys[hwm].mask = tkey->mask; in pack_key()
138 sel->keys[hwm].off = tkey->off; in pack_key()
139 sel->keys[hwm].at = tkey->at; in pack_key()
140 sel->keys[hwm].offmask = tkey->offmask; in pack_key()
141 sel->keys[hwm].shift = tkey->shift; in pack_key()
155 sel->nkeys++; in pack_key()
[all …]
Dm_csum.c39 parse_csum_args(int *argc_p, char ***argv_p, struct tc_csum *sel) in parse_csum_args() argument
51 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_IPV4HDR; in parse_csum_args()
54 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_ICMP; in parse_csum_args()
57 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_IGMP; in parse_csum_args()
60 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_TCP; in parse_csum_args()
63 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_UDP; in parse_csum_args()
66 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_UDPLITE; in parse_csum_args()
69 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_SCTP; in parse_csum_args()
91 struct tc_csum sel = {}; in parse_csum() local
101 if (parse_csum_args(&argc, &argv, &sel)) { in parse_csum()
[all …]
Dm_nat.c44 parse_nat_args(int *argc_p, char ***argv_p, struct tc_nat *sel) in parse_nat_args() argument
54 sel->flags |= TCA_NAT_FLAG_EGRESS; in parse_nat_args()
63 sel->old_addr = addr.data[0]; in parse_nat_args()
64 sel->mask = htonl(~0u << (32 - addr.bitlen)); in parse_nat_args()
71 sel->new_addr = addr.data[0]; in parse_nat_args()
87 struct tc_nat sel = {}; in parse_nat() local
97 if (parse_nat_args(&argc, &argv, &sel)) { in parse_nat()
118 parse_action_control_dflt(&argc, &argv, &sel.action, false, TC_ACT_OK); in parse_nat()
123 if (get_u32(&sel.index, *argv, 10)) { in parse_nat()
134 addattr_l(n, MAX_MSG, TCA_NAT_PARMS, &sel, sizeof(sel)); in parse_nat()
[all …]
/external/mesa3d/src/intel/tools/tests/gen8/
Dsel.asm1 (-f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x3f800000UD { align1 1Q };
2 (+f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x00000000UD { align1 1Q };
3 (+f0.0) sel(8) g24<1>UQ g66<4,4,1>UQ g40<4,4,1>UQ { align1 1Q };
4 (+f0.0) sel(8) g36<1>UQ g50<4,4,1>UQ g31<4,4,1>UQ { align1 2Q };
5 sel.ge(8) g10<1>F g4<8,8,1>F g5<8,8,1>F { align1 1Q };
6 (+f0.0) sel(16) g23<1>UD g39<8,8,1>UD g41<8,8,1>UD { align1 1H };
7 (-f0.0) sel(16) g11<1>UD g58<8,8,1>UD 0x00000000UD { align1 1H };
8 sel.l(8) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1Q };
9 sel.l(16) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1H };
10 sel.ge(8) g3<1>D g2<0,1,0>D -1D { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen9/
Dsel.asm1 (-f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x3f800000UD { align1 1Q };
2 (+f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x00000000UD { align1 1Q };
3 (+f0.0) sel(8) g24<1>UQ g66<4,4,1>UQ g40<4,4,1>UQ { align1 1Q };
4 (+f0.0) sel(8) g36<1>UQ g50<4,4,1>UQ g31<4,4,1>UQ { align1 2Q };
5 sel.ge(8) g17<1>F (abs)g16<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q };
6 sel.ge(16) g37<1>F (abs)g35<8,8,1>F 0x3f800000F /* 1F */ { align1 1H };
7 (+f0.0) sel(16) g26<1>UD g31<8,8,1>UD g33<8,8,1>UD { align1 1H };
8 (-f0.0) sel(16) g1<1>UD g55<8,8,1>UD 0x00000000UD { align1 1H };
9 sel.l(8) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1Q };
10 sel.l(16) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1H };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dsel.asm1 (+f0.0.any4h) sel(8) g7<1>UD g9<4>UD g8<4>UD { align16 };
2 (+f0.0) sel(8) g10<1>.xyUD g7<4>.xyyyUD g3<0>.zwwwUD { align16 };
3 (+f0.0.all4h) sel(8) g6<1>UD g6<4>UD g7<4>UD { align16 };
4 (+f0.0) sel(16) g6<1>UD g40<8,8,1>UD g46<8,8,1>UD { align1 compr };
5 (+f0.0) sel(16) m3<1>UD g30<8,8,1>UD 0x3f800000UD { align1 compr4 };
6 (+f0.0) sel(16) g10<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
7 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
8 (+f0.0.x) sel(8) g6<1>.xUD g6<4>.yUD 0x41a80000UD { align16 };
9 (-f0.0.x) sel(8) g6<1>.xUD g6<4>.xUD 0x41b80000UD { align16 };
10 (+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4/
Dsel.asm1 (+f0.0.any4h) sel(8) g7<1>UD g9<4>UD g8<4>UD { align16 };
2 (+f0.0) sel(8) g10<1>.xyUD g7<4>.xyyyUD g3<0>.zwwwUD { align16 };
3 (+f0.0.all4h) sel(8) g6<1>UD g6<4>UD g7<4>UD { align16 };
4 (+f0.0) sel(16) g6<1>UD g40<8,8,1>UD g46<8,8,1>UD { align1 compr };
5 (+f0.0) sel(16) g6<1>UD g30<8,8,1>UD 0x3f800000UD { align1 compr };
6 (+f0.0) sel(16) g10<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
7 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
8 (+f0.0) sel(8) g4<1>.yF g5<4>.xF 0x0F /* 0F */ { align16 };
9 (-f0.0.z) sel(8) g4<1>.zUD g6<4>.xUD 0x00000000UD { align16 };
10 (+f0.0.x) sel(8) g6<1>.xUD g6<4>.yUD 0x41a80000UD { align16 };
[all …]
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Dcombine-min-max.ll11 %sel = select i1 %cmp, i32 %a, i32 %b
12 ret i32 %sel
20 %sel = select i1 %cmp, i64 %b, i64 %a
21 ret i64 %sel
32 %sel = select i1 %cmp, i16 %a, i16 %b
33 ret i16 %sel
40 %sel = select i1 %cmp, i16 %a, i16 %b
41 ret i16 %sel
48 %sel = select i1 %cmp, i16 %a, i16 %b
49 ret i16 %sel
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dcombine-min-max.ll11 %sel = select i1 %cmp, i32 %a, i32 %b
12 ret i32 %sel
20 %sel = select i1 %cmp, i64 %b, i64 %a
21 ret i64 %sel
34 %sel = select i1 %cmp, i16 %a, i16 %b
35 ret i16 %sel
47 %sel = select i1 %cmp, i32 %a, i32 %b
48 ret i32 %sel
55 %sel = select i1 %cmp, i32 %a, i32 %b
56 ret i32 %sel
[all …]
/external/llvm/test/Transforms/InstCombine/
Dunordered-fcmp-select.ll5 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %b, float %a
6 ; CHECK-NEXT: ret float %sel
9 %sel = select i1 %cmp, float %a, float %b
10 ret float %sel
15 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %b, float %a
16 ; CHECK-NEXT: ret float %sel
19 %sel = select i1 %cmp, float %a, float %b
20 ret float %sel
25 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %a, float %b
26 ; CHECK-NEXT: ret float %sel
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Dvselect-cost.ll14 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
15 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
16 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
17 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
18 %sel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
19 ret <2 x i64> %sel
24 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
25 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
26 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
27 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dcmpsel.ll11 %sel = select i1 %cmp, i8 %val3, i8 %val4
12 ret i8 %sel
16 ; CHECK: cost of 1 for instruction: %sel = select i1 %cmp, i8 %val3, i8 %val4
22 %sel = select i1 %cmp, i16 %val3, i16 %val4
23 ret i16 %sel
27 ; CHECK: cost of 1 for instruction: %sel = select i1 %cmp, i16 %val3, i16 %val4
33 %sel = select i1 %cmp, i32 %val3, i32 %val4
34 ret i32 %sel
38 ; CHECK: cost of 1 for instruction: %sel = select i1 %cmp, i32 %val3, i32 %val4
44 %sel = select i1 %cmp, i64 %val3, i64 %val4
[all …]
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_shaders.c45 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es, in si_get_ir_cache_key() argument
52 if (sel->nir_binary) { in si_get_ir_cache_key()
53 ir_binary = sel->nir_binary; in si_get_ir_cache_key()
54 ir_size = sel->nir_size; in si_get_ir_cache_key()
56 assert(sel->nir); in si_get_ir_cache_key()
59 nir_serialize(&blob, sel->nir, true); in si_get_ir_cache_key()
71 if (sel->nir) in si_get_ir_cache_key()
73 if (si_get_wave_size(sel->screen, sel->info.stage, ngg, es, false, false) == 32) in si_get_ir_cache_key()
75 if (sel->info.stage == MESA_SHADER_FRAGMENT && in si_get_ir_cache_key()
77 sel->info.base.fs.needs_helper_invocations && in si_get_ir_cache_key()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dselect_const.ll15 %sel = select i1 %cond, i32 0, i32 1
16 ret i32 %sel
24 %sel = select i1 %cond, i32 0, i32 1
25 ret i32 %sel
34 %sel = select i1 %cond, i32 0, i32 1
35 ret i32 %sel
45 %sel = select i1 %cond, i32 1, i32 0
46 ret i32 %sel
53 %sel = select i1 %cond, i32 1, i32 0
54 ret i32 %sel
[all …]
/external/libnl/lib/route/cls/
Du32.c136 struct tc_u32_sel *sel; in u32_msg_parser() local
144 sel = u->cu_selector->d_data; in u32_msg_parser()
146 (sel->nkeys * sizeof(uint64_t)); in u32_msg_parser()
227 static void print_selector(struct nl_dump_params *p, struct tc_u32_sel *sel, in print_selector() argument
233 if (sel->hmask || sel->hoff) { in print_selector()
238 nl_dump(p, " hash at %u & 0x%x", sel->hoff, sel->hmask); in print_selector()
241 if (sel->flags & (TC_U32_OFFSET | TC_U32_VAROFFSET)) { in print_selector()
242 nl_dump(p, " offset at %u", sel->off); in print_selector()
244 if (sel->flags & TC_U32_VAROFFSET) in print_selector()
246 sel->offoff, ntohs(sel->offmask), sel->offshift); in print_selector()
[all …]

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