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Searched refs:setDesc (Results 1 – 25 of 239) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break; in runOnMachineFunction()
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break; in runOnMachineFunction()
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break; in runOnMachineFunction()
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break; in runOnMachineFunction()
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break; in runOnMachineFunction()
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break; in runOnMachineFunction()
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break; in runOnMachineFunction()
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break; in runOnMachineFunction()
86 case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break; in runOnMachineFunction()
87 case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted = true; break; in runOnMachineFunction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp81 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
85 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
89 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
93 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
97 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
101 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
105 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
109 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
113 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
117 Def->setDesc(TII.get(GT_U_I32)); in runOnMachineFunction()
[all …]
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp81 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
85 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
89 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
93 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
97 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
101 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
105 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
109 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
113 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
117 Def->setDesc(TII.get(GT_U_I32)); in runOnMachineFunction()
[all …]
/external/angle/src/libANGLE/renderer/d3d/d3d11/
DMappedSubresourceVerifier11.h27 void setDesc(const D3D11_TEXTURE2D_DESC &desc);
28 void setDesc(const D3D11_TEXTURE3D_DESC &desc);
48 inline void MappedSubresourceVerifier11::setDesc(const D3D11_TEXTURE2D_DESC &desc) {} in setDesc() function
49 inline void MappedSubresourceVerifier11::setDesc(const D3D11_TEXTURE3D_DESC &desc) {} in setDesc() function
DMappedSubresourceVerifier11.cpp47 void MappedSubresourceVerifier11::setDesc(const D3D11_TEXTURE2D_DESC &desc) in setDesc() function in rx::MappedSubresourceVerifier11
60 void MappedSubresourceVerifier11::setDesc(const D3D11_TEXTURE3D_DESC &desc) in setDesc() function in rx::MappedSubresourceVerifier11
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIOptimizeExecMasking.cpp184 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
189 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
195 MI.setDesc(TII.get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
201 MI.setDesc(TII.get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
207 MI.setDesc(TII.get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
213 MI.setDesc(TII.get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
219 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
225 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
DSIShrinkInstructions.cpp207 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
217 MI.setDesc(NewDesc); in shrinkScalarCompare()
296 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
375 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
634 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); in runOnMachineFunction()
679 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
699 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
701 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
735 MIB->setDesc(TII.get(Opcodes.ADDrr)); in selectGlobal()
747 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
750 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad)); in selectGlobal()
756 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
758 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp95 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
100 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
111 MI.setDesc(TII->get(Opcode)); in shortenOn0()
122 MI.setDesc(TII->get(Opcode)); in shortenOn01()
135 MI.setDesc(TII->get(Opcode)); in shortenOn001()
168 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
DSystemZInstrInfo.cpp83 EarlierMI->setDesc(get(HighOpcode)); in splitMove()
84 MI->setDesc(get(LowOpcode)); in splitMove()
99 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
114 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode)); in expandRIPseudo()
131 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
135 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); in expandRIEPseudo()
149 MI.setDesc(get(Opcode)); in expandRXYPseudo()
174 Ear1MI->setDesc(get(SystemZ::EAR)); in expandLoadStackGuard()
180 SllgMI->setDesc(get(SystemZ::SLLG)); in expandLoadStackGuard()
186 Ear2MI->setDesc(get(SystemZ::EAR)); in expandLoadStackGuard()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp94 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
99 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
110 MI.setDesc(TII->get(Opcode)); in shortenOn0()
121 MI.setDesc(TII->get(Opcode)); in shortenOn01()
134 MI.setDesc(TII->get(Opcode)); in shortenOn001()
167 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
322 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
DSystemZPostRewrite.cpp95 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
97 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
146 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
148 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
223 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
DSystemZInstrInfo.cpp111 EarlierMI->setDesc(get(HighOpcode)); in splitMove()
112 MI->setDesc(get(LowOpcode)); in splitMove()
127 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
142 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode)); in expandRIPseudo()
159 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
167 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); in expandRIEPseudo()
181 MI.setDesc(get(Opcode)); in expandRXYPseudo()
191 MI.setDesc(get(Opcode)); in expandLOCPseudo()
236 MI->setDesc(get(SystemZ::LG)); in expandLoadStackGuard()
662 UseMI.setDesc(get(NewUseOpc)); in FoldImmediate()
[all …]
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp95 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
100 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
111 MI.setDesc(TII->get(Opcode)); in shortenOn0()
122 MI.setDesc(TII->get(Opcode)); in shortenOn01()
135 MI.setDesc(TII->get(Opcode)); in shortenOn001()
168 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
195 MI.setDesc(TII->get(Opcode)); in shortenFusedFPOp()
365 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
DSystemZPostRewrite.cpp95 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
97 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
146 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
148 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
223 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
679 MIB->setDesc(TII.get(Opc)); in selectGlobal()
717 MIB->setDesc(TII.get(Opc)); in selectGlobal()
737 MIB->setDesc(TII.get(Opcodes.ADDrr)); in selectGlobal()
749 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
752 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad)); in selectGlobal()
758 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
760 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs)); in selectGlobal()
809 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
[all …]
/external/llvm-project/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
112 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
139 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp103 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
141 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
112 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
139 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIOptimizeExecMasking.cpp185 MI.setDesc(TII.get(AMDGPU::COPY)); in removeTerminatorBit()
191 MI.setDesc(TII.get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
197 MI.setDesc(TII.get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
203 MI.setDesc(TII.get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
209 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
215 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
DSIShrinkInstructions.cpp206 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
216 MI.setDesc(NewDesc); in shrinkScalarCompare()
295 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
370 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
583 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); in runOnMachineFunction()
657 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
677 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
679 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp305 I.setDesc(TII.get(X86::COPY)); in selectCopy()
537 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
573 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
625 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
677 I.setDesc(TII.get(NewOpc)); in selectConstant()
702 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
768 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
877 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1128 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr)); in selectExtract()
1130 I.setDesc(TII.get(X86::VEXTRACTF128rr)); in selectExtract()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp304 I.setDesc(TII.get(X86::COPY)); in selectCopy()
536 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
572 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
624 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
676 I.setDesc(TII.get(NewOpc)); in selectConstant()
701 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
767 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
922 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1173 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr)); in selectExtract()
1175 I.setDesc(TII.get(X86::VEXTRACTF128rr)); in selectExtract()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64CompressJumpTables.cpp130 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
136 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CompressJumpTables.cpp130 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
135 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()

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