| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineLoopUtils.cpp | 56 MO.setReg(R); in PeelSingleBlockLoop()
68 Use->setReg(R); in PeelSingleBlockLoop()
77 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
92 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
99 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineLoopUtils.cpp | 57 MO.setReg(R); in PeelSingleBlockLoop()
69 Use->setReg(R); in PeelSingleBlockLoop()
78 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
93 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
100 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 245 MI->getOperand(0).setReg(KilledProdReg); in processBlock()
246 MI->getOperand(1).setReg(KilledProdReg); in processBlock()
247 MI->getOperand(3).setReg(AddendSrcReg); in processBlock()
264 MI->getOperand(2).setReg(AddendSrcReg); in processBlock()
269 MI->getOperand(2).setReg(OtherProdReg); in processBlock()
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| D | PPCMIPeephole.cpp | 156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
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| D | PPCVSXCopy.cpp | 125 SrcMO.setReg(NewVReg); in processBlock()
147 SrcMO.setReg(NewVReg); in processBlock()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
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| D | PPCMIPeephole.cpp | 424 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
425 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
446 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
514 MI.getOperand(1).setReg(ShiftOp1); in simplifyCode()
556 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
616 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
660 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
918 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in simplifyCode()
946 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in simplifyCode()
1436 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
[all …]
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| D | PPCVSXCopy.cpp | 114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
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| D | PPCVSXCopy.cpp | 114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
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| D | PPCMIPeephole.cpp | 585 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
586 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
607 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
675 MI.getOperand(1).setReg(ShiftOp1); in simplifyCode()
719 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
779 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
823 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
1461 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
1462 CMPI2->getOperand(2).setReg(Op1); in eliminateRedundantCompare()
1476 CMPI2->getOperand(I).setReg(SrcReg); in eliminateRedundantCompare()
[all …]
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyDebugValueManager.cpp | 34 DBI->getDebugOperand(0).setReg(Reg); in updateReg()
43 Clone->getDebugOperand(0).setReg(NewReg); in clone()
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| D | WebAssemblyFixBrTableDefaults.cpp | 65 MI.getOperand(0).setReg(ExtMI->getOperand(1).getReg()); in fixBrTableIndex()
74 MI.getOperand(0).setReg(Reg32); in fixBrTableIndex()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyDebugValueManager.cpp | 34 DBI->getOperand(0).setReg(Reg); in updateReg()
43 Clone->getOperand(0).setReg(NewReg); in clone()
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| D | WebAssemblyPeephole.cpp | 67 MO.setReg(NewReg); in maybeRewriteToDrop()
123 MO.setReg(NewReg); in maybeRewriteToFallthrough()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
360 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
372 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
503 MO.setReg(High); in HexagonProcessInstruction()
515 MO.setReg(High); in HexagonProcessInstruction()
528 MO.setReg(High); in HexagonProcessInstruction()
561 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
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| D | HexagonPeephole.cpp | 252 MI.getOperand(0).setReg(PeepholeSrc); in runOnMachineFunction()
282 MI.getOperand(PR).setReg(POrig); in runOnMachineFunction()
305 Dst.setReg(Src.getReg()); in ChangeOpInto()
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZCopyPhysRegs.cpp | 95 MI->getOperand(1).setReg(Tmp); in visitMBB()
101 MI->getOperand(0).setReg(Tmp); in visitMBB()
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| D | SystemZPostRewrite.cpp | 125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
230 SrcMO.setReg(DstReg); in selectMI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
404 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
542 MO.setReg(High); in HexagonProcessInstruction()
554 MO.setReg(High); in HexagonProcessInstruction()
568 MO.setReg(High); in HexagonProcessInstruction()
601 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
404 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
542 MO.setReg(High); in HexagonProcessInstruction()
554 MO.setReg(High); in HexagonProcessInstruction()
568 MO.setReg(High); in HexagonProcessInstruction()
601 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZPostRewrite.cpp | 125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
230 SrcMO.setReg(DstReg); in selectMI()
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| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 399 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
438 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
472 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
473 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
470 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
470 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
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