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Searched refs:setRegClass (Results 1 – 25 of 59) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSILowerI1Copies.cpp88 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass); in runOnMachineFunction()
144 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass); in runOnMachineFunction()
DSIFixSGPRCopies.cpp204 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
62 setRegClass(Reg, NewRC); in constrainRegClass()
87 setRegClass(Reg, NewRC); in recomputeRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
142 setRegClass(Reg, NewRC); in recomputeRegClass()
/external/llvm-project/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
142 setRegClass(Reg, NewRC); in recomputeRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
275 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
807 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
DAMDGPUInstructionSelector.cpp134 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
270 MRI->setRegClass(Src0.getReg(), RC); in selectG_AND_OR_XOR()
272 MRI->setRegClass(Src1.getReg(), RC); in selectG_AND_OR_XOR()
432 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
658 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1157 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC_W_SIDE_EFFECTS()
1191 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
1611 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
DSILowerI1Copies.cpp571 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
692 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
DAMDGPURegisterBankInfo.cpp912 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass); in executeInWaterfallLoop()
913 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
914 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
931 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass); in executeInWaterfallLoop()
944 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass); in executeInWaterfallLoop()
945 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
DAMDGPULegalizerInfo.cpp1667 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
2385 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
2386 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
2409 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp221 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
273 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
847 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
DSILowerI1Copies.cpp575 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
696 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
DAMDGPUInstructionSelector.cpp166 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
440 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
916 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1223 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
1772 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2405 MRI->setRegClass( in selectG_AMDGPU_ATOMIC_CMPXCHG()
2444 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp424 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1218 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1222 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1235 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1244 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2307 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2309 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp417 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1318 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1322 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1335 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1344 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2434 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2436 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp416 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1315 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1319 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1332 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1341 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2420 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2422 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/external/swiftshader/third_party/subzero/src/
DIceVariableSplitting.cpp106 NewVar->setRegClass(Var->getRegClass()); in makeLinked()
DIceTargetLoweringX86BaseImpl.h2498 T_AhRcvr->setRegClass(RCX86_IsAhRcvr);
2576 T_AhRcvr->setRegClass(RCX86_IsAhRcvr);
3081 T_1->setRegClass(RCX86_Is32To8);
3082 T_2->setRegClass(RCX86_IsTrunc8Rcvr);
3111 T_1->setRegClass(RCX86_Is32To8);
3112 T_2->setRegClass(RCX86_IsTrunc8Rcvr);
4686 T_1->setRegClass(RCX86_Is32To8);
4687 T_2->setRegClass(RCX86_IsTrunc8Rcvr);
7862 Reg->setRegClass(RCX86_IsTrunc8Rcvr);
7867 SrcTruncable->setRegClass(RCX86_Is64To8);
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64LegalizerInfo.cpp792 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
812 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h616 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp1307 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1309 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1311 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86DomainReassignment.cpp511 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp146 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h670 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/external/llvm-project/llvm/lib/Target/X86/
DX86DomainReassignment.cpp507 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()

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