| /external/deqp-deps/SPIRV-Tools/source/val/ |
| D | validate_bitwise.cpp | 43 const uint32_t shift_type = _.GetOperandTypeId(inst, 3); in BitwisePass() local
61 if (!shift_type || in BitwisePass()
62 (!_.IsIntScalarType(shift_type) && !_.IsIntVectorType(shift_type))) in BitwisePass()
67 if (_.GetDimension(shift_type) != result_dimension) in BitwisePass()
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| /external/swiftshader/third_party/SPIRV-Tools/source/val/ |
| D | validate_bitwise.cpp | 43 const uint32_t shift_type = _.GetOperandTypeId(inst, 3); in BitwisePass() local
61 if (!shift_type || in BitwisePass()
62 (!_.IsIntScalarType(shift_type) && !_.IsIntVectorType(shift_type))) in BitwisePass()
67 if (_.GetDimension(shift_type) != result_dimension) in BitwisePass()
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| /external/angle/third_party/vulkan-deps/spirv-tools/src/source/val/ |
| D | validate_bitwise.cpp | 43 const uint32_t shift_type = _.GetOperandTypeId(inst, 3); in BitwisePass() local
61 if (!shift_type || in BitwisePass()
62 (!_.IsIntScalarType(shift_type) && !_.IsIntVectorType(shift_type))) in BitwisePass()
67 if (_.GetDimension(shift_type) != result_dimension) in BitwisePass()
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| /external/tensorflow/tensorflow/compiler/tf2xla/kernels/ |
| D | roll_op.cc | 53 xla::PrimitiveType shift_type = ctx->input_xla_type(1); in Compile() local
74 ctx->builder(), shift_type, input_shape.dim_size(cur_axis)); in Compile()
84 input_shape.dims(), xla::Zero(ctx->builder(), shift_type)); in Compile()
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| /external/capstone/bindings/ocaml/ |
| D | arm64.ml | 8 shift_type: int; RecordField
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| D | test_arm64.ml | 47 if op.shift.shift_type != _ARM64_SFT_INVALID && op.shift.shift_value > 0 then
49 op.shift.shift_type op.shift.shift_value;
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| D | arm.ml | 13 shift_type: int; (* TODO: covert this to pattern like arm_op_value? *) RecordField
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| D | test_arm.ml | 55 if op.shift.shift_type != _ARM_SFT_INVALID && op.shift.shift_value > 0 then
57 op.shift.shift_type op.shift.shift_value;
|
| /external/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.h | 448 ARM_ShifterType shift_type);
452 ARM_ShifterType shift_type);
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| D | EmulateInstructionARM.cpp | 3749 ARM_ShifterType shift_type) { in EmulateShiftImm() argument
3768 if (shift_type == SRType_ROR && use_encoding == eEncodingT1) { in EmulateShiftImm()
3778 if (shift_type == SRType_ROR) in EmulateShiftImm()
3789 if (shift_type == SRType_RRX) in EmulateShiftImm()
3810 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3811 shift_type = SRType_RRX; in EmulateShiftImm()
3820 (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
3822 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success); in EmulateShiftImm()
3839 ARM_ShifterType shift_type) { in EmulateShiftReg() argument
3893 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success); in EmulateShiftReg()
|
| /external/gemmlowp/meta/generators/ |
| D | neon_emitter_64.py | 928 def EmitVShl(self, shift_type, destination, source, shift): argument
930 _AppendType(shift_type, destination),
931 _AppendType(shift_type, source), _AppendType('i32', shift))
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| D | neon_emitter.py | 525 def EmitVShl(self, shift_type, destination, source, shift): argument
526 self.EmitOp3('vshl.%s' % shift_type, destination, source, shift)
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 486 Shift shift_type, in ShiftOperand() argument
496 switch (shift_type) { in ShiftOperand()
1874 Shift shift_type = static_cast<Shift>(instr->GetShiftDP()); in VisitLogicalShifted() local
1878 shift_type, in VisitLogicalShifted()
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| D | disasm-aarch64.cc | 10470 const char *shift_type[] = {"lsl", "lsr", "asr", "ror"}; in SubstituteShiftField() local
10472 shift_type[instr->GetShiftDP()], in SubstituteShiftField()
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| D | simulator-aarch64.h | 2831 Shift shift_type,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 1396 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1400 let Inst{11-10} = shift_type;
1403 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1404 def Wr : BaseShift<shift_type, GPR32, asm> {
1408 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 1937 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1941 let Inst{11-10} = shift_type;
1944 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1945 def Wr : BaseShift<shift_type, GPR32, asm> {
1949 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 2073 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
2077 let Inst{11-10} = shift_type;
2080 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
2081 def Wr : BaseShift<shift_type, GPR32, asm> {
2085 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
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| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 12829 Shift shift_type, in BitwiseShiftWideElementsHelper() argument
12841 switch (shift_type) { in BitwiseShiftWideElementsHelper()
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| /external/cpuinfo/test/dmesg/ |
| D | galaxy-s6.log | 210 [ 0.259555] [6: swapper/0: 1] (ASV_TBL_BASE+0x0C)[8] shift_type = 0
|