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/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dashift-left-right.ll7 %shl1 = shl i32 16, %a
9 %ret = mul i32 %shl1, %shl2
17 %shl1 = ashr i32 16, %a
19 %ret = mul i32 %shl1, %shl2
/external/llvm/test/CodeGen/Hexagon/
Dashift-left-right.ll7 %shl1 = shl i32 16, %a
9 %ret = mul i32 %shl1, %shl2
17 %shl1 = ashr i32 16, %a
19 %ret = mul i32 %shl1, %shl2
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dlds_atomic_f32.ll19 %shl1 = shl i32 %idx.add, 4
21 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
40 %shl1 = shl i32 %idx.add, 4
42 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
61 %shl1 = shl i32 %idx.add, 4
63 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
Dshl_add_ptr.ll304 %shl1 = shl i32 %idx.add, 4
306 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)*
321 %shl1 = shl i32 %idx.add, 4
323 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)*
338 %shl1 = shl i32 %idx.add, 5
340 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)*
356 %shl1 = shl i32 %idx.add, 3
358 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
374 %shl1 = shl i32 %idx.add, 4
376 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
[all …]
Dlocal-atomics-fp.ll42 %shl1 = shl i32 %idx.add, 4
44 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
63 %shl1 = shl i32 %idx.add, 4
65 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
/external/llvm-project/llvm/test/CodeGen/Mips/
Dmicromips-shift.ll18 %shl1 = shl i32 %1, 10
19 store i32 %shl1, i32* @d, align 4
/external/llvm/test/CodeGen/Mips/
Dmicromips-shift.ll18 %shl1 = shl i32 %1, 10
19 store i32 %shl1, i32* @d, align 4
/external/llvm-project/llvm/test/CodeGen/Hexagon/loop-idiom/
Dpmpy.ll20 %shl1 = shl i64 %conv, %sh_prom
21 %xor = xor i64 %shl1, %R.06
/external/llvm-project/llvm/test/CodeGen/X86/
Dvec_shift4.ll5 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
6 ; X86-LABEL: shl1:
14 ; X64-LABEL: shl1:
Dpr47482.ll30 %shl1 = select i1 %2, i32 2, i32 0
32 %or = or i32 %3, %shl1
Dsse2-vector-shifts.ll290 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
291 ret <4 x i32> %shl1
300 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
301 ret <4 x i32> %shl1
317 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
318 ret <4 x i32> %shl1
354 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
355 ret <4 x i32> %shl1
DtargetLoweringGeneric.ll23 %shl1 = shl i32 %xor3, %i32In4
24 %sub1 = sub i32 %or2, %shl1
Dpr22338.ll62 %shl1 = shl i32 %sext, %sel1
64 %tobool = icmp eq i32 %shl1, 0
Dlegalize-shift-64.ll166 %shl1 = shl i64 1, %sh_prom
167 %cmp = icmp ne i64 %shl1, 4294967296
/external/llvm/test/CodeGen/X86/
Dsse2-vector-shifts.ll288 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
289 ret <4 x i32> %shl1
298 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
299 ret <4 x i32> %shl1
309 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
310 ret <4 x i32> %shl1
344 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
345 ret <4 x i32> %shl1
Dvec_shift4.ll5 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
6 ; X32-LABEL: shl1:
14 ; X64-LABEL: shl1:
DtargetLoweringGeneric.ll23 %shl1 = shl i32 %xor3, %i32In4
24 %sub1 = sub i32 %or2, %shl1
Dlegalize-shift-64.ll78 %shl1 = shl i64 1, %sh_prom
79 %cmp = icmp ne i64 %shl1, 4294967296
/external/llvm/test/CodeGen/PowerPC/
Dldtoc-inv.ll23 %shl1 = shl i32 %0, %step_size
24 %idxprom2 = sext i32 %shl1 to i64
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dldtoc-inv.ll23 %shl1 = shl i32 %0, %step_size
24 %idxprom2 = sext i32 %shl1 to i64
/external/llvm-project/llvm/test/CodeGen/RISCV/
Drv32Zbp.ll192 %shl1 = and i32 %and1, -1431655766
196 %or1b = or i32 %or1, %shl1
255 %shl1 = and i64 %and1, -6148914691236517206
259 %or1b = or i64 %or1, %shl1
378 %shl1 = and i32 %and1, -1431655766
382 %or1b = or i32 %or1, %shl1
441 %shl1 = and i64 %and1, -6148914691236517206
445 %or1b = or i64 %or1, %shl1
490 %shl1 = and i32 %and1, -858993460
494 %or1b = or i32 %or1, %shl1
[all …]
Drv64Zbp.ll209 %shl1 = and i32 %and1, -1431655766
213 %or1b = or i32 %or1, %shl1
282 %shl1 = and i64 %and1, -6148914691236517206
286 %or1b = or i64 %or1, %shl1
415 %shl1 = and i32 %and1, -1431655766
419 %or1b = or i32 %or1, %shl1
488 %shl1 = and i64 %and1, -6148914691236517206
492 %or1b = or i64 %or1, %shl1
540 %shl1 = and i32 %and1, -858993460
544 %or1b = or i32 %or1, %shl1
[all …]
/external/llvm/test/Transforms/InstCombine/
Dnsw.ll31 ; CHECK-LABEL: @shl1(
34 define i64 @shl1(i64 %X, i64* %P) nounwind {
Dbswap.ll133 %shl1 = and i32 %and2, 65280
134 %or = or i32 %and1, %shl1
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dnsw.ll35 define i64 @shl1(i64 %X, i64* %P) {
36 ; CHECK-LABEL: @shl1(

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