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Searched refs:shl2 (Results 1 – 25 of 38) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dashift-left-right.ll8 %shl2 = shl i32 %b, 16
9 %ret = mul i32 %shl1, %shl2
18 %shl2 = ashr i32 %b, 16
19 %ret = mul i32 %shl1, %shl2
Dexpand-condsets-extend.ll30 %shl2.i322 = or i64 undef, -9223372036854775808
49 %shr.i263 = lshr i64 %shl2.i322, 32
76 %shl2.i207 = shl i64 %aSig0.3554, 61
77 %or.i209 = or i64 %shl2.i207, 0
Dtail-dup-subreg-map.ll59 %shl2.i = shl i64 %aSig0.2, 15
61 %or.i = or i64 %shl2.i, %shr.i
/external/llvm/test/CodeGen/Hexagon/
Dashift-left-right.ll8 %shl2 = shl i32 %b, 16
9 %ret = mul i32 %shl1, %shl2
18 %shl2 = ashr i32 %b, 16
19 %ret = mul i32 %shl1, %shl2
Dtail-dup-subreg-map.ll59 %shl2.i = shl i64 %aSig0.2, 15
61 %or.i = or i64 %shl2.i, %shr.i
/external/llvm-project/llvm/test/DebugInfo/X86/
Dpr34545.ll28 %shl2 = shl i32 %shl, %2
29 …tail call void @llvm.dbg.value(metadata i32 %shl2, metadata !18, metadata !DIExpression()), !dbg !…
30 store i32 %shl2, i32* @var
31 ret i32 %shl2
Ddbg-value-transfer-order.ll73 %shl2 = shl i32 %add, 3, !dbg !55
74 %idxprom = zext i32 %shl2 to i64, !dbg !57
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dbitreverse.ll116 %shl2 = shl i32 %v, 16
117 %or = or i32 %shr1, %shl2
120 %shl2.1 = shl i32 %or, 8
121 %and3.1 = and i32 %shl2.1, -16711936
125 %shl2.2 = shl i32 %or.1, 4
126 %and3.2 = and i32 %shl2.2, -252645136
130 %shl2.3 = shl i32 %or.2, 2
131 %and3.3 = and i32 %shl2.3, -858993460
135 %shl2.4 = shl i32 %or.3, 1
136 %and3.4 = and i32 %shl2.4, -1431655766
/external/llvm/test/CodeGen/AArch64/
Deon.ll27 %shl2 = shl i64 %xor, %xor1
28 ret i64 %shl2
/external/llvm-project/llvm/test/CodeGen/AArch64/
Deon.ll30 %shl2 = shl i64 %xor, %xor1
31 ret i64 %shl2
Dswap-compare-operands.ll525 %shl2 = shl i64 %conv2, 3
526 %na2 = sub i64 0, %shl2
589 %shl2 = shl i64 %conv2, 3
590 %na2 = sub i64 0, %shl2
/external/llvm-project/llvm/test/CodeGen/X86/
Dvec_shift4.ll27 define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
28 ; X86-LABEL: shl2:
51 ; X64-LABEL: shl2:
Dpr27202.ll62 %shl2 = and i64 %and1, 56
64 %or = or i64 %and3, %shl2
Dpr22338.ll63 %shl2 = shl i32 %sext, %sel2
71 ret i32 %shl2
Dfold-tied-op.ll39 %shl2 = shl i64 %3, 2
41 %or3 = or i64 %shl2, %shr
/external/llvm/test/CodeGen/X86/
Dvec_shift4.ll33 define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
34 ; X32-LABEL: shl2:
57 ; X64-LABEL: shl2:
Dfold-tied-op.ll39 %shl2 = shl i64 %3, 2
41 %or3 = or i64 %shl2, %shr
Dx86-shifts.ll42 define <2 x i64> @shl2(<2 x i64> %A) nounwind {
44 ; CHECK: shl2
Dmmx-coalescing.ll18 %shl2 = shl i32 1, %D
/external/llvm-project/llvm/test/CodeGen/Mips/
Dmips64extins.ll34 %shl2 = shl i64 %j, 8
35 %and = and i64 %shl2, 261888
/external/llvm/test/CodeGen/Mips/
Dmips64extins.ll34 %shl2 = shl i64 %j, 8
35 %and = and i64 %shl2, 261888
/external/llvm-project/llvm/test/CodeGen/RISCV/
Drv32Zbp.ll198 %shl2 = and i32 %and2, -858993460
202 %or2b = or i32 %or2, %shl2
261 %shl2 = and i64 %and2, -3689348814741910324
265 %or2b = or i64 %or2, %shl2
384 %shl2 = and i32 %and2, -252645136
388 %or2b = or i32 %or2, %shl2
447 %shl2 = and i64 %and2, -1085102592571150096
451 %or2b = or i64 %or2, %shl2
496 %shl2 = and i32 %and2, -252645136
500 %or2b = or i32 %or2, %shl2
[all …]
Drv64Zbp.ll215 %shl2 = and i32 %and2, -858993460
219 %or2b = or i32 %or2, %shl2
288 %shl2 = and i64 %and2, -3689348814741910324
292 %or2b = or i64 %or2, %shl2
421 %shl2 = and i32 %and2, -252645136
425 %or2b = or i32 %or2, %shl2
494 %shl2 = and i64 %and2, -1085102592571150096
498 %or2b = or i64 %or2, %shl2
546 %shl2 = and i32 %and2, -252645136
550 %or2b = or i32 %or2, %shl2
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dunaligned-floats.ll28 %shl2 = shl nuw nsw i32 %conv1, 16
29 %add = or i32 %shl2, %shl
/external/llvm-project/llvm/test/Transforms/LowerTypeTests/
Dimport.ll138 ; CHECK-NEXT: [[shl2:%.*]] = shl i32 1, [[and]]
139 …86-NEXT: [[and2:%.*]] = and i32 ptrtoint ([0 x i8]* @__typeid_inline5_inline_bits to i32), [[shl2]]
140 ; ARM-NEXT: [[and2:%.*]] = and i32 123, [[shl2]]
166 ; CHECK-NEXT: [[shl2:%.*]] = shl i64 1, [[and]]
167 …86-NEXT: [[and2:%.*]] = and i64 ptrtoint ([0 x i8]* @__typeid_inline6_inline_bits to i64), [[shl2]]
168 ; ARM-NEXT: [[and2:%.*]] = and i64 1000000000000, [[shl2]]

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