| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 235 define i32 @shsub16(i32 %a, i32 %b) nounwind {
236 ; CHECK-LABEL: shsub16
237 ; CHECK: shsub16 r0, r0, r1
238 %tmp = call i32 @llvm.arm.shsub16(i32 %a, i32 %b)
455 declare i32 @llvm.arm.shsub16(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 64 M(shsub16) \
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| D | test-assembler-cond-rd-rn-rm-a32.cc | 65 M(shsub16) \
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 257 shsub16 r0, r1, r2 label
688 # CHECK-NEXT: 1 1 1.00 shsub16 r0, r1, r2
1128 …0 - - - - 1.00 - - - - - - shsub16 r0, r1, r2
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| D | m4-int.s | 265 shsub16 r0, r1, r2 label
711 # CHECK-NEXT: 1 1 1.00 shsub16 r0, r1, r2
1149 # CHECK-NEXT: 1.00 shsub16 r0, r1, r2
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| D | cortex-a57-basic-instructions.s | 564 shsub16 r4, r8, r2
1434 # CHECK-NEXT: 1 2 1.00 shsub16 r4, r8, r2
2311 # CHECK-NEXT: - - - - 1.00 - - - shsub16 r4, r8, r2
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| D | cortex-a57-thumb.s | 586 shsub16 r4, r8, r2
1494 # CHECK-NEXT: 1 2 1.00 shsub16 r4, r8, r2
2408 # CHECK-NEXT: - - - - 1.00 - - - shsub16 r4, r8, r2
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 637 0x72,0x4f,0x38,0xe6 = shsub16 r4, r8, r2
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3043 void shsub16(Condition cond, Register rd, Register rn, Register rm);
3044 void shsub16(Register rd, Register rn, Register rm) { in shsub16() function
3045 shsub16(al, rd, rn, rm); in shsub16()
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| D | disasm-aarch32.h | 1081 void shsub16(Condition cond, Register rd, Register rn, Register rm);
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2381 shsub16 r4, r8, r2
2386 @ CHECK: shsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xe6]
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| D | basic-thumb2-instructions.s | 2456 shsub16 r4, r8, r2
2462 @ CHECK: shsub16 r4, r8, r2 @ encoding: [0xd8,0xfa,0x22,0xf4]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2351 shsub16 r4, r8, r2
2356 @ CHECK: shsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xe6]
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| D | basic-thumb2-instructions.s | 2247 shsub16 r4, r8, r2
2253 @ CHECK: shsub16 r4, r8, r2 @ encoding: [0xd8,0xfa,0x22,0xf4]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1559 # CHECK: shsub16 r4, r8, r2
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| D | thumb2.txt | 1731 # CHECK: shsub16 r4, r8, r2
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1731 # CHECK: shsub16 r4, r8, r2
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| D | basic-arm-instructions.txt | 1559 # CHECK: shsub16 r4, r8, r2
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 730 { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */
5956 { /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 730 { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */
5956 { /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2179 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
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| D | ARMInstrInfo.td | 3608 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2482 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2531 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9900 "shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003smc\006smla"
11099 …{ 1086 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2…
11100 …{ 1086 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { M…
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