Home
last modified time | relevance | path

Searched refs:si4 (Results 1 – 5 of 5) sorted by relevance

/external/llvm-project/mlir/integration_test/Dialect/Vector/CPU/
Dtest-reductions-si4.mlir14 %0 = vector.reduction "add", %v : vector<16xsi4> into si4
15 vector.print %0 : si4
18 %1 = vector.reduction "mul", %v : vector<16xsi4> into si4
19 vector.print %1 : si4
22 %2 = vector.reduction "min", %v : vector<16xsi4> into si4
23 vector.print %2 : si4
26 %3 = vector.reduction "max", %v : vector<16xsi4> into si4
27 vector.print %3 : si4
30 %4 = vector.reduction "and", %v : vector<16xsi4> into si4
31 vector.print %4 : si4
[all …]
/external/curl/lib/
Dconnect.c247 struct sockaddr_in *si4 = (struct sockaddr_in *)&sa; in bindlocal() local
412 (Curl_inet_pton(AF_INET, myhost, &si4->sin_addr) > 0)) { in bindlocal()
413 si4->sin_family = AF_INET; in bindlocal()
414 si4->sin_port = htons(port); in bindlocal()
439 si4->sin_family = AF_INET; in bindlocal()
440 si4->sin_port = htons(port); in bindlocal()
468 si4->sin_port = ntohs(port); in bindlocal()
/external/llvm-project/mlir/test/IR/
Dparser.mlir64 // CHECK: func private @sint_types(si2, si4) -> (si7, si1023)
65 func private @sint_types(si2, si4) -> (si7, si1023)
/external/llvm-project/mlir/test/Conversion/VectorToLLVM/
Dvector-to-llvm.mlir455 func @vector_print_scalar_si4(%arg0: si4) {
456 vector.print %arg0 : si4
/external/hyphenation-patterns/ga/
Dhyph-ga.pat.txt482 .si4