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Searched refs:simm13 (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td388 // inc simm13, rd -> add rd, simm13, rd
389 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
394 // inccc simm13, rd -> addcc rd, simm13, rd
395 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
400 // dec simm13, rd -> sub rd, simm13, rd
401 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
406 // deccc simm13, rd -> subcc rd, simm13, rd
407 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
411 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
415 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
[all …]
DSparcInstr64Bit.td63 // The ALU instructions want their simm13 operands as i32 immediates.
67 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
98 // (sllx simm13, n)
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
179 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
[all …]
DSparcInstrInfo.td83 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
317 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
318 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
319 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
331 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
332 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
440 let rd = 8, rs1 = 0, simm13 = 3 in
656 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
657 "andn $rs1, $simm13, $rd", []>;
666 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
[all …]
DSparcInstrFormats.td146 bits<13> simm13;
152 let Inst{12-0} = simm13;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td388 // inc simm13, rd -> add rd, simm13, rd
389 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
394 // inccc simm13, rd -> addcc rd, simm13, rd
395 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
400 // dec simm13, rd -> sub rd, simm13, rd
401 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
406 // deccc simm13, rd -> subcc rd, simm13, rd
407 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
411 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
415 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
[all …]
DSparcInstr64Bit.td63 // The ALU instructions want their simm13 operands as i32 immediates.
67 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
98 // (sllx simm13, n)
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
179 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
[all …]
DSparcInstrInfo.td83 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
317 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
318 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
319 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
331 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
332 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
440 let rd = 8, rs1 = 0, simm13 = 3 in
656 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
657 "andn $rs1, $simm13, $rd", []>;
666 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
[all …]
DSparcInstrFormats.td146 bits<13> simm13;
152 let Inst{12-0} = simm13;
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td389 // inc simm13, rd -> add rd, simm13, rd
390 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
395 // inccc simm13, rd -> addcc rd, simm13, rd
396 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
401 // dec simm13, rd -> sub rd, simm13, rd
402 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
407 // deccc simm13, rd -> subcc rd, simm13, rd
408 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
412 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
416 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
[all …]
DSparcInstr64Bit.td64 // The ALU instructions want their simm13 operands as i32 immediates.
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
99 // (sllx simm13, n)
103 // (xor (sllx sethi), simm13)
104 // (sllx (xor sethi, simm13))
113 // (or (sllx sethi), (or sethi, simm13))
114 // (xnor (sllx sethi), (or sethi, simm13))
120 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
180 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
[all …]
DSparcInstrInfo.td76 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
297 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
298 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
299 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
420 let rd = 0, rs1 = 1, simm13 = 3 in
657 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
658 "andn $rs1, $simm13, $rd", []>;
667 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
[all …]
DSparcInstrFormats.td147 bits<13> simm13;
153 let Inst{12-0} = simm13;
/external/capstone/arch/Sparc/
DSparcDisassembler.c258 unsigned simm13 = 0; in DecodeMem() local
261 simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); in DecodeMem()
278 MCOperand_CreateImm0(MI, simm13); in DecodeMem()
379 unsigned simm13 = 0; in DecodeJMPL() local
382 simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); in DecodeJMPL()
398 MCOperand_CreateImm0(MI, simm13); in DecodeJMPL()
415 unsigned simm13 = 0; in DecodeReturn() local
417 simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); in DecodeReturn()
428 MCOperand_CreateImm0(MI, simm13); in DecodeReturn()
446 unsigned simm13 = 0; in DecodeSWAP() local
[all …]
DSparcGenAsmWriter.inc3925 // (ORri IntRegs:$rd, G0, i32imm:$simm13)
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp387 unsigned simm13 = 0; in DecodeMem() local
389 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeMem()
407 MI.addOperand(MCOperand::createImm(simm13)); in DecodeMem()
542 unsigned simm13 = 0; in DecodeJMPL() local
544 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeJMPL()
560 MI.addOperand(MCOperand::createImm(simm13)); in DecodeJMPL()
575 unsigned simm13 = 0; in DecodeReturn() local
577 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeReturn()
588 MI.addOperand(MCOperand::createImm(simm13)); in DecodeReturn()
606 unsigned simm13 = 0; in DecodeSWAP() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp379 unsigned simm13 = 0; in DecodeMem() local
381 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeMem()
399 MI.addOperand(MCOperand::createImm(simm13)); in DecodeMem()
534 unsigned simm13 = 0; in DecodeJMPL() local
536 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeJMPL()
552 MI.addOperand(MCOperand::createImm(simm13)); in DecodeJMPL()
567 unsigned simm13 = 0; in DecodeReturn() local
569 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeReturn()
580 MI.addOperand(MCOperand::createImm(simm13)); in DecodeReturn()
598 unsigned simm13 = 0; in DecodeSWAP() local
[all …]
/external/llvm-project/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp379 unsigned simm13 = 0; in DecodeMem() local
381 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeMem()
399 MI.addOperand(MCOperand::createImm(simm13)); in DecodeMem()
534 unsigned simm13 = 0; in DecodeJMPL() local
536 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeJMPL()
552 MI.addOperand(MCOperand::createImm(simm13)); in DecodeJMPL()
567 unsigned simm13 = 0; in DecodeReturn() local
569 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeReturn()
580 MI.addOperand(MCOperand::createImm(simm13)); in DecodeReturn()
598 unsigned simm13 = 0; in DecodeSWAP() local
[all …]
/external/llvm/docs/
DWritingAnLLVMBackend.rst814 [(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;
/external/llvm-project/llvm/docs/
DWritingAnLLVMBackend.rst814 [(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;