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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td642 bits<16> simm16;
649 let Inst{15-0} = simm16;
658 let Inst{15-0} = simm16;
673 (ins s16imm:$simm16),
674 "$sdst, $simm16",
680 (ins sopp_brtarget:$simm16, SReg_32:$sdst),
681 "$sdst, $simm16",
694 (ins SReg_32:$sdst, s16imm:$simm16),
695 (ins SReg_32:$sdst, u16imm:$simm16)),
696 "$sdst, $simm16", []>,
[all …]
DSIModeRegister.cpp245 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSOPInstructions.td707 bits<16> simm16;
714 let Inst{15-0} = simm16;
723 let Inst{15-0} = simm16;
738 (ins s16imm:$simm16),
739 "$sdst, $simm16",
745 (ins sopp_brtarget:$simm16, SReg_32:$sdst),
746 "$sdst, $simm16",
759 (ins SReg_32:$sdst, s16imm:$simm16),
760 (ins SReg_32:$sdst, u16imm:$simm16)),
761 "$sdst, $simm16", []>,
[all …]
DSIModeRegister.cpp252 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
DSIInsertWaitcnts.cpp1097 auto W = TII->getNamedOperand(*II, AMDGPU::OpName::simm16)->getImm(); in generateWaitcntInstBefore()
1146 unsigned ICnt = TII->getNamedOperand(*II, AMDGPU::OpName::simm16) in generateWaitcntInstBefore()
1152 TII->getNamedOperand(*II, AMDGPU::OpName::simm16)->setImm(Wait.VsCnt); in generateWaitcntInstBefore()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.getreg.ll12 define amdgpu_kernel void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
22 define amdgpu_kernel void @readnone_s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds …
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td399 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
405 (ins hwreg:$simm16), " $sdst, $simm16"
411 (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst"
417 (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
424 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
430 let simm16 = 0;
438 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
439 [(br bb:$simm16)]> {
445 0x00000004, (ins sopp_brtarget:$simm16),
446 "s_cbranch_scc0 $simm16"
[all …]
DSIInstrFormats.td215 bits <16> simm16;
217 let Inst{15-0} = simm16;
225 bits <16> simm16;
228 let Inst{15-0} = simm16;
237 bits <16> simm16;
239 let Inst{15-0} = simm16;
DSIInstrInfo.td929 def "" : SOPK_Pseudo <opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
932 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
933 opName#" $sdst, $simm16">;
935 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
936 opName#" $sdst, $simm16">;
947 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
952 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
958 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
959 " $sdst, $simm16"
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.getreg.ll7 define void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrInfo.td23 let MIOperandInfo = (ops CPU16Regs, simm16);
35 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
41 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
64 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
82 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
96 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
105 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
121 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
160 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
193 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
[all …]
DMipsInstrInfo.td959 // Like uimm16_64 but coerces simm16 to uimm16.
979 // Like uimm16_64 but coerces simm16 to uimm16.
1057 // Like simm16 but coerces uimm16 to simm16.
1124 let MIOperandInfo = (ops ptr_rc, simm16);
1169 let MIOperandInfo = (ops ptr_rc, simm16);
1670 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
2039 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
2041 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
2529 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
2534 (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
[all …]
DMicroMipsInstrInfo.td141 let MIOperandInfo = (ops ptr_rc, simm16);
722 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
724 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
726 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
728 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.td24 let MIOperandInfo = (ops CPU16Regs, simm16);
36 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
42 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
65 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
83 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
97 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
106 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
122 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
161 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
194 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
[all …]
DMipsInstrInfo.td741 // Like uimm16_64 but coerces simm16 to uimm16.
762 // Like uimm16_64 but coerces simm16 to uimm16.
837 // Like simm16 but coerces uimm16 to simm16.
936 let MIOperandInfo = (ops ptr_rc, simm16);
988 let MIOperandInfo = (ops ptr_rc, simm16);
995 let MIOperandInfo = (ops ptr_rc, simm16);
1424 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
1689 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1691 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
2137 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
[all …]
DMicroMipsInstrInfo.td129 let MIOperandInfo = (ops ptr_rc, simm16);
678 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
680 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
682 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
684 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1105 (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1107 (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
DMicroMips64r6InstrInfo.td80 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
89 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
DMips32r6InstrInfo.td306 dag InOperandList = (ins simm16:$imm);
319 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td23 let MIOperandInfo = (ops CPU16Regs, simm16);
35 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
41 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
64 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
82 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
96 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
105 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
121 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
160 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
193 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
[all …]
DMipsInstrInfo.td959 // Like uimm16_64 but coerces simm16 to uimm16.
979 // Like uimm16_64 but coerces simm16 to uimm16.
1057 // Like simm16 but coerces uimm16 to simm16.
1124 let MIOperandInfo = (ops ptr_rc, simm16);
1169 let MIOperandInfo = (ops ptr_rc, simm16);
1670 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
2038 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
2040 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
2528 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
2533 (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
[all …]
DMicroMipsInstrInfo.td141 let MIOperandInfo = (ops ptr_rc, simm16);
722 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
724 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
726 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
728 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc10680 simm16 = 73,
13924 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13926 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13927 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13930 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13932 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13933 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13948 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16,
13950 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16,
13968 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::simm16,
[all …]
/external/mesa3d/docs/relnotes/
D13.0.3.rst115 - radeonsi: allow specifying simm16 of emit_waitcnt at call sites
/external/llvm/test/CodeGen/Mips/
Dinlineasm-operand-code.ll36 ; This is _also_ -3 because uimm16 values are silently coerced to simm16 when
/external/llvm-project/llvm/test/CodeGen/Mips/
Dinlineasm-operand-code.ll36 ; This is _also_ -3 because uimm16 values are silently coerced to simm16 when

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