| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_resource.c | 349 res->aux.surf.size_B = 0; in iris_resource_disable_aux()
351 res->aux.extra_aux.surf.size_B = 0; in iris_resource_disable_aux()
454 const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ? in map_aux_addresses()
460 res->surf.size_B, format_bits); in map_aux_addresses()
610 assert(res->aux.extra_aux.surf.size_B > 0 && in iris_resource_configure_aux()
612 assert(res->aux.surf.size_B > 0 && in iris_resource_configure_aux()
757 res->aux.surf.size_B); in iris_resource_init_aux_buf()
761 0, res->aux.extra_aux.surf.size_B); in iris_resource_init_aux_buf()
784 assert(res->bo->size >= aux_res->aux.offset + res->aux.surf.size_B); in import_aux_info()
937 uint64_t bo_size = res->surf.size_B; in iris_resource_create_with_modifiers()
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| D | iris_draw.c | 332 .size_B = sizeof(grid->grid), in iris_update_grid_size_resource()
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| D | iris_program.c | 179 .size_B = buf->buffer_size - res->offset, in iris_upload_ubo_ssbo_surf_state()
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| D | iris_state.c | 2183 .size_B = final_size, in fill_buffer_surface_state()
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| /external/mesa3d/src/intel/isl/ |
| D | isl.c | 1664 uint64_t size_B; in isl_surf_init_s() local
1666 size_B = (uint64_t) row_pitch_B * phys_total_el.h; in isl_surf_init_s()
1698 size_B = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch_B; in isl_surf_init_s()
1737 if (size_B > (uint64_t) 1 << 31) in isl_surf_init_s()
1746 if (size_B > (uint64_t) 1 << 38) in isl_surf_init_s()
1750 if (size_B > (uint64_t) 1 << 44) in isl_surf_init_s()
1768 .size_B = size_B, in isl_surf_init_s()
1906 if (mcs_surf->size_B > 0) in isl_surf_get_mcs_surf()
2102 if (aux_surf->size_B > 0 && in isl_surf_get_ccs_surf()
2103 (extra_aux_surf == NULL || extra_aux_surf->size_B > 0)) { in isl_surf_get_ccs_surf()
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| D | isl.h | 1279 uint64_t size_B; member
1433 uint64_t size_B; member
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| D | isl_surface_state.c | 815 uint64_t buffer_size = info->size_B; in isl_genX()
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_image.c | 136 assert(surf->isl.size_B > 0); /* isl surface must be initialized */ in add_surface()
149 image->size = surf->offset + surf->isl.size_B; in add_surface()
150 image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset; in add_surface()
367 assert(image->planes[plane].aux_surface.isl.size_B == 0); in add_aux_surface_if_supported()
511 image->planes[plane].aux_surface.isl.size_B = 0; in add_aux_surface_if_supported()
639 (image->planes[plane].aux_surface.isl.size_B > 0 ? in make_surface()
640 image->planes[plane].aux_surface.isl.size_B : in make_surface()
641 image->planes[plane].surface.isl.size_B)) <= in make_surface()
1184 layout->size = surface->isl.size_B; in anv_GetImageSubresourceLayout()
1738 if (image->planes[plane].shadow_surface.isl.size_B > 0 && in anv_image_fill_surface_state()
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| D | anv_blorp.c | 277 if (image->planes[plane].shadow_surface.isl.size_B == 0) in get_blorp_surf_for_anv_shadow_image()
472 isl_format_for_size(unsigned size_B) in isl_format_for_size() argument
475 switch (size_B) { in isl_format_for_size()
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| D | genX_cmd_buffer.c | 665 if (image->planes[plane].shadow_surface.isl.size_B > 0 && in transition_stencil_buffer()
1148 if (image->planes[plane].shadow_surface.isl.size_B > 0 && in transition_color_buffer()
5920 if (image->planes[plane].shadow_surface.isl.size_B > 0 && in cmd_buffer_end_subpass()
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| D | anv_device.c | 4357 .size_B = range, in anv_fill_buffer_surface_state()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_mipmap_tree.c | 409 } else if (need_to_retile_as_x(brw, mt->surf.size_B, mt->surf.tiling)) { in make_surface()
421 assert(mt->surf.size_B % mt->surf.row_pitch_B == 0); in make_surface()
425 mt->surf.size_B, in make_surface()
619 assert(bo->size >= mt->surf.size_B); in intel_miptree_create_for_bo()
736 assert(temp_ccs_surf.size_B <= image->bo->size - image->aux_offset); in create_ccs_buf_for_image()
1458 uint64_t size = aux_surf->size_B; in intel_alloc_aux_buffer()
1505 memset(map, memset_value, aux_surf->size_B); in intel_alloc_aux_buffer()
1540 assert(mt->surf.size_B > 0); in intel_miptree_level_enable_hiz()
1585 aux_surf.size_B = 0; in intel_miptree_alloc_aux()
1640 if (aux_surf.size_B == 0) in intel_miptree_alloc_aux()
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| D | intel_screen.c | 785 aux_surf.size_B = 0; in intel_create_image_common()
798 surf.size_B + aux_surf.size_B, in intel_create_image_common()
811 if (aux_surf.size_B) { in intel_create_image_common()
812 image->aux_offset = surf.size_B; in intel_create_image_common()
814 image->aux_size = aux_surf.size_B; in intel_create_image_common()
1177 const int end = offsets[index] + surf.size_B; in intel_create_image_from_fds_common()
1215 image->aux_size = aux_surf.size_B; in intel_create_image_from_fds_common()
1217 const int end = image->aux_offset + aux_surf.size_B; in intel_create_image_from_fds_common()
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| D | brw_wm_surface_state.c | 645 .size_B = buffer_size, in brw_emit_buffer_surface_state()
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | conv_grad_input_ops.h | 627 const size_t size_B = filter_total_size * dims.out_depth;
631 const size_t work_unit_size = size_A + size_B + size_C;
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| D | conv_grad_ops_3d.cc | 404 const int64 size_B = filter_total_size * dims.out_depth; in Compute() local
408 const int64 work_unit_size = size_A + size_B + size_C; in Compute()
877 const int64 size_B = output_image_size * dims.out_depth; in Compute() local
881 const int64 work_unit_size = size_A + size_B + size_C; in Compute()
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| D | conv_grad_filter_ops.cc | 515 const size_t size_B = output_image_size * dims.out_depth; in Compute() local
519 const size_t work_unit_size = size_A + size_B + size_C; in Compute()
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| /external/mesa3d/src/intel/blorp/ |
| D | blorp_blit.c | 2807 isl_format_for_size(unsigned size_B) in isl_format_for_size() argument
2809 switch (size_B) { in isl_format_for_size()
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| /external/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 1731 - anv: Replace aux_surface.isl.size_B checks with aux_usage checks
1745 - anv: Replace one more aux_surface.isl.size_B check
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