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/external/llvm/test/MC/AMDGPU/
Dmubuf.s33 buffer_load_dword v1, off, s[4:7], s1 offset:4 slc
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
69 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc
81 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
85 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
141 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
[all …]
Dflat.s28 flat_load_dword v1, v[3:4] glc slc
38 flat_load_dword v1, v[3:4] glc slc tfe
43 flat_load_dword v1, v[3:4] slc
48 flat_load_dword v1, v[3:4] slc tfe
66 flat_store_dword v[3:4], v1 glc slc
74 flat_store_dword v[3:4], v1 glc slc tfe
78 flat_store_dword v[3:4], v1 slc
82 flat_store_dword v[3:4], v1 slc tfe
100 flat_atomic_add v1 v[3:4], v5 glc slc
110 flat_atomic_add v1 v[3:4], v5 glc slc tfe
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dmubuf.s33 buffer_load_dword v1, off, s[4:7], s1 offset:4 slc
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
69 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc
81 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
85 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
141 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
[all …]
Dflat-gfx9.s28 flat_load_dword v1, v[3:4] offset:4 glc slc
32 flat_atomic_add v[3:4], v5 offset:8 slc
36 flat_atomic_add v[3:4], v5 inst_offset:8 slc
44 flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 slc
52 flat_atomic_cmpswap v[1:2], v[3:4] slc
66 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc
74 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc slc
85 flat_atomic_cmpswap v0, v[1:2], v[3:4] slc
Dflat-gfx10.s19 flat_load_dword v1, v[3:4] offset:4 glc slc
22 flat_load_dword v1, v[3:4] offset:4 glc slc dlc
25 flat_atomic_add v[3:4], v5 offset:8 slc
31 flat_atomic_cmpswap v[1:2], v[3:4] offset:2047 slc
37 flat_atomic_cmpswap v[1:2], v[3:4] slc
49 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 glc slc
55 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc slc
64 flat_atomic_cmpswap v0, v[1:2], v[3:4] slc
Dmubuf-gfx10.s3 buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds
6 buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds dlc
9 buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc
42 buffer_atomic_fmin_x2 v[0:1], off, s[0:3], s0 offset:4095 slc
Dgfx1030_new.s9 global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc
12 global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc
18 global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc
27 global_atomic_csub v2, v0, v2, s[2:3] offset:100 glc slc
45 buffer_atomic_csub v5, off, s[8:11], s3 glc slc
Dflat.s28 flat_load_dword v1, v[3:4] glc slc
41 flat_store_dword v[3:4], v1 glc slc
46 flat_store_dword v[3:4], v1 slc
55 flat_atomic_add v1, v[3:4], v5 offset:0 glc slc
60 flat_atomic_add v[3:4], v5 slc
Dmimg.s39 image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
72 image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
257 image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da
291 image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da
414 image_atomic_add v8, v4, s[8:15] dmask:0x1 slc
418 image_atomic_add v9, v5, s[8:15] dmask:0x1 unorm glc slc lwe da
/external/adhd/cras/src/server/
Dcras_hfp_iodev.c36 struct hfp_slc_handle *slc; member
51 (hfp_slc_get_selected_codec(hfpio->slc) == HFP_CODEC_ID_MSBC) ? in update_supported_formats()
149 hfp_slc_codec_connection_setup(hfpio->slc); in configure_dev()
152 hfp_slc_get_selected_codec(hfpio->slc)); in configure_dev()
157 hfpio->device, sk, hfp_slc_get_selected_codec(hfpio->slc)); in configure_dev()
160 err = hfp_info_start(sk, mtu, hfp_slc_get_selected_codec(hfpio->slc), in configure_dev()
169 hfp_set_call_status(hfpio->slc, 1); in configure_dev()
186 hfp_set_call_status(hfpio->slc, 0); in close_dev()
204 hfp_event_speaker_gain(hfpio->slc, volume); in set_hfp_volume()
266 return hfp_slc_is_hsp(hfpio->slc); in hfp_iodev_is_hsp()
[all …]
Dcras_hfp_alsa_iodev.c31 struct hfp_slc_handle *slc; member
104 hfp_slc_get_selected_codec(hfp_alsa_io->slc)); in hfp_alsa_configure_dev()
110 hfp_set_call_status(hfp_alsa_io->slc, 1); in hfp_alsa_configure_dev()
121 hfp_set_call_status(hfp_alsa_io->slc, 0); in hfp_alsa_close_dev()
196 hfp_event_speaker_gain(hfp_alsa_io->slc, volume); in hfp_alsa_set_volume()
238 struct hfp_slc_handle *slc, in hfp_alsa_iodev_create() argument
254 hfp_alsa_io->slc = slc; in hfp_alsa_iodev_create()
294 if ((hfp_slc_get_selected_codec(hfp_alsa_io->slc) == in hfp_alsa_iodev_create()
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dmubuf_vi.txt12 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x…
21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0…
33 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x52,0xe0,0x…
42 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
75 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x…
84 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04…
96 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x72,0xe0,0x00,0…
105 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe…
[all …]
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX7.rst197 …data<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
198 …data<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
199 …data<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
200 …data<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
201 …:ref:`b32x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
202 …:ref:`b64x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
203 …:ref:`u32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
204 …:ref:`u64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
205 …:ref:`f32x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
206 …:ref:`f64x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
DAMDGPUAsmGFX10.rst424 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
425 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
426 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
427 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
428 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
429 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
430 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
431 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
432 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
433 …ef:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
DAMDGPUAsmGFX9.rst212 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
213 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
214 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
215 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
216 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
217 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
218 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
219 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
220 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
221 …ef:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
DAMDGPUAsmGFX8.rst202 …data<amdgpu_synid8_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
203 …data<amdgpu_synid8_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
204 …data<amdgpu_synid8_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
205 …data<amdgpu_synid8_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
206 …:ref:`b32x2<amdgpu_synid8_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
207 …:ref:`b64x2<amdgpu_synid8_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
208 …:ref:`u32<amdgpu_synid8_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
209 …:ref:`u64<amdgpu_synid8_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
210 …:ref:`u32<amdgpu_synid8_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
211 …:ref:`u64<amdgpu_synid8_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dmubuf_vi.txt12 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x…
21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0…
33 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x52,0xe0,0x…
42 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
75 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x…
84 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04…
96 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x72,0xe0,0x00,0…
105 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dmemory-legalizer-flat-nontemporal.ll14 ; GFX7-NEXT: flat_load_dword v0, v[0:1] glc slc
27 ; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] slc
40 ; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] slc
53 ; SKIP-CACHE-INV-NEXT: flat_load_dword v0, v[0:1] glc slc
75 ; GFX7-NEXT: flat_load_dword v2, v[2:3] glc slc
89 ; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] slc
103 ; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] slc
118 ; SKIP-CACHE-INV-NEXT: flat_load_dword v2, v[2:3] glc slc
144 ; GFX7-NEXT: flat_store_dword v[2:3], v0 glc slc
157 ; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2 slc
[all …]
Dmemory-legalizer-private-nontemporal.ll21 ; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
38 ; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc slc
57 ; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
74 ; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
91 ; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
117 ; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
135 ; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc slc
154 ; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
171 ; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
189 ; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
[all …]
Dmemory-legalizer-global-nontemporal.ll90 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 glc slc
103 ; GFX7-NEXT: flat_load_dword v2, v[2:3] glc slc
116 ; GFX10-WGP-NEXT: global_load_dword v0, v0, s[0:1] slc
127 ; GFX10-CU-NEXT: global_load_dword v0, v0, s[0:1] slc
144 ; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 glc slc
169 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 glc slc
181 ; GFX7-NEXT: flat_store_dword v[0:1], v2 glc slc
192 ; GFX10-WGP-NEXT: global_store_dword v0, v1, s[2:3] slc
203 ; GFX10-CU-NEXT: global_store_dword v0, v1, s[2:3] slc
217 ; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[4:7], 0 glc slc
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DFLATInstructions.td91 bits<1> slc;
116 let Inst{17} = slc;
145 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
147 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
166 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
167 …" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
200 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
201 (ins VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
202 … "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
216 …(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc…
[all …]
DMIMGInstructions.td228 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
231 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
241 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
254 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
321 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
324 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
334 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
336 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td124 SDTCisVT<11, i32>, // slc(imm)
554 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
2859 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2861 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2873 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2875 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2919 bits<1> slc;
3030 SCSrc_32:$soffset, offset:$offset, slc:$slc),
3031 name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$slc", [], 0
3037 slc:$slc),
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.load.dword.ll10 ; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
11 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
12 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
13 …uffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
15 …{{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
/external/llvm-project/mlir/lib/Conversion/VectorToROCDL/
DVectorToROCDL.cpp34 Value &offsetSizeInBytes, Value &glc, Value &slc) { in replaceTransferOpWithMubuf() argument
36 xferOp, vecTy, dwordConfig, vindex, offsetSizeInBytes, glc, slc); in replaceTransferOpWithMubuf()
44 Value &offsetSizeInBytes, Value &glc, Value &slc) { in replaceTransferOpWithMubuf() argument
48 offsetSizeInBytes, glc, slc); in replaceTransferOpWithMubuf()

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