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Searched refs:sllv (Results 1 – 25 of 134) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dshl.ll98 ; MIPS2-NEXT: sllv $1, $4, $1
106 ; MIPS32-NEXT: sllv $1, $4, $1
114 ; MIPS32R2-NEXT: sllv $1, $4, $1
121 ; MIPS32R6-NEXT: sllv $1, $4, $1
128 ; MIPS3-NEXT: sllv $1, $4, $1
136 ; MIPS4-NEXT: sllv $1, $4, $1
144 ; MIPS64-NEXT: sllv $1, $4, $1
152 ; MIPS64R2-NEXT: sllv $1, $4, $1
159 ; MIPS64R6-NEXT: sllv $1, $4, $1
166 ; MMR3-NEXT: sllv $1, $4, $2
[all …]
Dashr.ll285 ; MIPS-NEXT: sllv $2, $4, $2
299 ; MIPS32-NEXT: sllv $2, $3, $2
313 ; 32R2-NEXT: sllv $2, $3, $2
333 ; 32R6-NEXT: sllv $4, $4, $6
365 ; MMR3-NEXT: sllv $3, $5, $3
385 ; MMR6-NEXT: sllv $4, $4, $6
402 ; MIPS-NEXT: sllv $10, $5, $9
417 ; MIPS-NEXT: sllv $1, $1, $8
428 ; MIPS-NEXT: sllv $1, $4, $9
443 ; MIPS-NEXT: sllv $24, $13, $24
[all …]
Dlshr.ll288 ; MIPS2-NEXT: sllv $2, $3, $2
301 ; MIPS32-NEXT: sllv $2, $3, $2
314 ; MIPS32R2-NEXT: sllv $2, $3, $2
327 ; MIPS32R6-NEXT: sllv $2, $3, $2
367 ; MMR3-NEXT: sllv $3, $5, $3
381 ; MMR6-NEXT: sllv $2, $3, $2
402 ; MIPS2-NEXT: sllv $10, $5, $12
417 ; MIPS2-NEXT: sllv $1, $1, $9
429 ; MIPS2-NEXT: sllv $1, $4, $12
443 ; MIPS2-NEXT: sllv $15, $12, $15
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s11 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
18 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
21 # CHECK-EL: sllv $2, $2, $3 # encoding: [0x43,0x00,0x10,0x10]
31 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
38 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
41 # CHECK-EB: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
48 sllv $2, $3, $5
Drotations32.s12 # CHECK-32: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-32: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-32: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-32: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
Drotations64.s12 # CHECK-64: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-64: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-64: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-64: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
Dmips64-alu-instructions.s20 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
48 sllv $2, $3, $5
Dmips-alu-instructions.s22 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
53 sllv $2, $3, $5
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s11 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
18 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
21 # CHECK-EL: sllv $2, $2, $3 # encoding: [0x43,0x00,0x10,0x10]
31 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
38 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
41 # CHECK-EB: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
48 sllv $2, $3, $5
Drotations32.s12 # CHECK-32: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-32: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-32: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-32: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
Drotations64.s12 # CHECK-64: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-64: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-64: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-64: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
Dmips64-alu-instructions.s20 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
48 sllv $2, $3, $5
Dmips-alu-instructions.s22 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
53 sllv $2, $3, $5
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dshl.ll47 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
52 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
56 ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
68 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
73 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
77 ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
88 ; ALL: sllv $2, $4, $5
98 ; M2: sllv $[[T0:[0-9]+]], $5, $7
102 ; M2: sllv $[[T2:[0-9]+]], $4, $7
115 ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
[all …]
Dlshr.ll89 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
102 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
113 ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
128 ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
139 ; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
Dashr.ll91 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
104 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
122 ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
134 ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
151 ; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfunnel-shift-rot.ll51 ; CHECK-NEXT: sllv $1, $4, $1
66 ; CHECK-NEXT: sllv $1, $4, $1
86 ; CHECK-BE-NEXT: sllv $9, $4, $2
91 ; CHECK-BE-NEXT: sllv $10, $5, $2
98 ; CHECK-BE-NEXT: sllv $3, $4, $3
114 ; CHECK-LE-NEXT: sllv $9, $5, $3
119 ; CHECK-LE-NEXT: sllv $10, $4, $3
126 ; CHECK-LE-NEXT: sllv $2, $5, $2
150 ; CHECK-NEXT: sllv $1, $6, $1
152 ; CHECK-NEXT: sllv $3, $5, $3
[all …]
Datomic-min-max.ll840 ; MIPS-NEXT: sllv $8, $1, $10
842 ; MIPS-NEXT: sllv $7, $5, $10
880 ; MIPSR6-NEXT: sllv $8, $1, $10
882 ; MIPSR6-NEXT: sllv $7, $5, $10
919 ; MM-NEXT: sllv $8, $1, $10
921 ; MM-NEXT: sllv $7, $5, $10
957 ; MMR6-NEXT: sllv $8, $1, $10
959 ; MMR6-NEXT: sllv $7, $5, $10
995 ; MIPSEL-NEXT: sllv $8, $1, $10
997 ; MIPSEL-NEXT: sllv $7, $5, $10
[all …]
Datomic.ll2252 ; MIPS32-NEXT: sllv $5, $1, $3
2254 ; MIPS32-NEXT: sllv $4, $4, $3
2287 ; MIPS32O0-NEXT: sllv $7, $1, $9
2289 ; MIPS32O0-NEXT: sllv $6, $4, $9
2326 ; MIPS32R2-NEXT: sllv $5, $1, $3
2328 ; MIPS32R2-NEXT: sllv $4, $4, $3
2358 ; MIPS32R6-NEXT: sllv $5, $1, $3
2360 ; MIPS32R6-NEXT: sllv $4, $4, $3
2391 ; MIPS32R6O0-NEXT: sllv $7, $1, $9
2393 ; MIPS32R6O0-NEXT: sllv $6, $4, $9
[all …]
Dfunnel-shift.ll26 ; CHECK-NEXT: sllv $1, $1, $2
37 ; CHECK-NEXT: sllv $1, $4, $1
78 ; CHECK-BE-NEXT: sllv $6, $19, $2
90 ; CHECK-BE-NEXT: sllv $6, $18, $2
102 ; CHECK-BE-NEXT: sllv $4, $5, $4
141 ; CHECK-LE-NEXT: sllv $6, $18, $3
153 ; CHECK-LE-NEXT: sllv $6, $19, $3
165 ; CHECK-LE-NEXT: sllv $4, $5, $4
307 ; CHECK-NEXT: sllv $2, $2, $3
349 ; CHECK-BE-NEXT: sllv $3, $5, $3
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll140 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
142 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
185 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
187 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
230 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
232 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
276 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
278 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
318 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dbitwise.ll276 ; MIPS32-NEXT: sllv $2, $4, $5
311 ; MIPS32-NEXT: sllv $2, $4, $1
359 ; MIPS32-NEXT: sllv $7, $3, $9
361 ; MIPS32-NEXT: sllv $9, $5, $9
363 ; MIPS32-NEXT: sllv $3, $3, $8
393 ; MIPS32-NEXT: sllv $7, $2, $7
428 ; MIPS32-NEXT: sllv $9, $2, $9
/external/google-breakpad/src/common/android/include/asm-mips/
Dasm.h123 #define INT_SLLV sllv
163 #define LONG_SLLV sllv
216 #define PTR_SLLV sllv
/external/llvm-project/llvm/test/MC/Mips/mips2/
Dvalid.s147 … sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
156 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
159 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
162 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/capstone/suite/MC/Mips/
Dmicromips-shift-instructions.s.cs3 0x65,0x00,0x10,0x10 = sllv $v0, $v1, $a1

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