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/external/llvm/test/MC/Mips/
Dmicromips-alu-instructions.s21 # CHECK-EL: slti $3, $3, 103 # encoding: [0x63,0x90,0x67,0x00]
22 # CHECK-EL: slti $3, $3, 103 # encoding: [0x63,0x90,0x67,0x00]
64 # CHECK-EB: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]
65 # CHECK-EB: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]
106 slti $3, $3, 103
Dmips64-alu-instructions.s22 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
23 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
51 slti $3, $3, 103
Dmips-alu-instructions.s24 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
25 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
56 slti $3, $3, 103
Dinstalias-imm-expanding.s198 # CHECK: slti $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x28]
200 # CHECK: slti $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x28]
207 # CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28]
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-alu-instructions.s21 # CHECK-EL: slti $3, $3, 103 # encoding: [0x63,0x90,0x67,0x00]
22 # CHECK-EL: slti $3, $3, 103 # encoding: [0x63,0x90,0x67,0x00]
64 # CHECK-EB: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]
65 # CHECK-EB: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]
106 slti $3, $3, 103
Dmips64-alu-instructions.s22 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
23 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
51 slti $3, $3, 103
Dmips-alu-instructions.s24 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
25 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
56 slti $3, $3, 103
Dmacro-sge.s11 # CHECK: slti $4, $4, 16 # encoding: [0x28,0x84,0x00,0x10]
14 # CHECK: slti $4, $5, 16 # encoding: [0x28,0xa4,0x00,0x10]
/external/llvm/test/CodeGen/Mips/
Dselgek.ll82 ; 16: slti ${{[0-9]+}}, 1000
85 ; 16: slti ${{[0-9]+}}, 1 # 16 bit inst
88 ; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
91 ; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
Dcmov.ll230 ; slti and conditional move.
242 ; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
247 ; 32-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767
255 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
260 ; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767
316 ; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
321 ; 32-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768
329 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
334 ; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768
418 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
[all …]
Dsetgek.ll14 ; 16: slti ${{[0-9]+}}, -32768
Dsetcc-se.ll26 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
59 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
/external/llvm-project/llvm/test/CodeGen/Mips/
Dselgek.ll82 ; 16: slti ${{[0-9]+}}, 1000
85 ; 16: slti ${{[0-9]+}}, 1 # 16 bit inst
88 ; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
91 ; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
Dcmov.ll230 ; slti and conditional move.
242 ; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
247 ; 32-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767
255 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
260 ; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767
316 ; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
321 ; 32-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768
329 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
334 ; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768
418 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
[all …]
Dsetltk.ll18 ; 16: slti $[[REGISTER:[0-9]+]], 10
19 ; MMR6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
Dsetcc-se.ll31 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
32 ; MMR6: slti $[[R0:[0-9]+]], $4, -32768
68 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
69 ; MMR6: slti $[[R0:[0-9]+]], $4, 32767
Df32-to-i64-single-float.ll31 ; CHECK-NEXT: slti $6, $2, 24
36 ; CHECK-NEXT: slti $2, $2, 0
Dselltk.ll88 ; 16: slti ${{[0-9]+}}, 3 # 16 bit inst
91 ; 16: slti ${{[0-9]+}}, 3 # 16 bit inst
/external/capstone/suite/MC/Mips/
Dmicromips-alu-instructions.s.cs14 0x63,0x90,0x67,0x00 = slti $v1, $v1, 103
15 0x63,0x90,0x67,0x00 = slti $v1, $v1, 103
Dmicromips-alu-instructions-EB.s.cs14 0x90,0x63,0x00,0x67 = slti $v1, $v1, 103
15 0x90,0x63,0x00,0x67 = slti $v1, $v1, 103
Dmips64-alu-instructions.s.cs17 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
18 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
Dmips-alu-instructions.s.cs19 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
20 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dalu32.ll30 define i32 @slti(i32 %a) nounwind {
31 ; RV32I-LABEL: slti:
33 ; RV32I-NEXT: slti a0, a0, 2
36 ; RV64I-LABEL: slti:
39 ; RV64I-NEXT: slti a0, a0, 2
Dalu8.ll25 define i8 @slti(i8 %a) nounwind {
26 ; RV32I-LABEL: slti:
30 ; RV32I-NEXT: slti a0, a0, 2
33 ; RV64I-LABEL: slti:
37 ; RV64I-NEXT: slti a0, a0, 2
Dalu16.ll25 define i16 @slti(i16 %a) nounwind {
26 ; RV32I-LABEL: slti:
30 ; RV32I-NEXT: slti a0, a0, 2
33 ; RV64I-LABEL: slti:
37 ; RV64I-NEXT: slti a0, a0, 2

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