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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dsmaxv-diagnostics.s7 smaxv d0, p7, z31.b define
12 smaxv d0, p7, z31.h define
17 smaxv d0, p7, z31.s define
22 smaxv v0.2d, p7, z31.d label
31 smaxv h0, p8, z31.h label
36 smaxv h0, p7.b, z31.h label
41 smaxv h0, p7.q, z31.h label
51 smaxv d0, p7, z31.d define
57 smaxv d0, p7, z31.d define
Dsmaxv.s10 smaxv b0, p7, z31.b label
16 smaxv h0, p7, z31.h label
22 smaxv s0, p7, z31.s label
28 smaxv d0, p7, z31.d define
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-smaxv.ll5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
9 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
20 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
32 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
42 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
53 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
[all …]
Darm64-neon-across.ll47 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
49 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
51 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
57 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
59 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
167 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
169 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
170 %0 = trunc i32 %smaxv.i to i8
176 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
178 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
[all …]
Dsve-int-reduce-pred.ll101 ; CHECK-NEXT: smaxv b0, p0, z0.b
104 %out = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %pg,
112 ; CHECK-NEXT: smaxv h0, p0, z0.h
115 %out = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %pg,
123 ; CHECK-NEXT: smaxv s0, p0, z0.s
126 %out = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %pg,
134 ; CHECK-NEXT: smaxv d0, p0, z0.d
137 %out = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %pg,
414 declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
415 declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
Daarch64-minmaxv.ll23 ; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
31 ; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
39 ; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
187 ; CHECK: smaxv {{h[0-9]+}}, [[V0]]
200 ; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
Dsve-fixed-length-int-reduce.ll338 ; CHECK: smaxv b0, v0.8b
347 ; CHECK: smaxv b0, v0.16b
357 ; CHECK-NEXT: smaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
369 ; VBITS_GE_512-NEXT: smaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
379 ; VBITS_EQ_256-DAG: smaxv b[[REDUCE:[0-9]+]], [[PG]], [[MAX]].b
391 ; VBITS_GE_1024-NEXT: smaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
403 ; VBITS_GE_2048-NEXT: smaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
414 ; CHECK: smaxv h0, v0.4h
423 ; CHECK: smaxv h0, v0.8h
433 ; CHECK-NEXT: smaxv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
[all …]
Dsve-int-reduce.ll339 ; CHECK-NEXT: smaxv b0, p0, z0.b
350 ; CHECK-NEXT: smaxv h0, p0, z0.h
361 ; CHECK-NEXT: smaxv s0, p0, z0.s
372 ; CHECK-NEXT: smaxv d0, p0, z0.d
Dsve-split-int-reduce.ll205 ; CHECK-NEXT: smaxv d0, p0, z0.d
/external/llvm/test/CodeGen/AArch64/
Darm64-smaxv.ll5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
9 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
20 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
32 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
42 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
53 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
[all …]
Darm64-neon-across.ll47 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
49 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
51 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
57 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
59 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
167 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
169 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
170 %0 = trunc i32 %smaxv.i to i8
176 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
178 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
[all …]
Daarch64-minmaxv.ll7 ; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
29 ; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
48 ; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
64 ; CHECK-NOT: smaxv
420 ; CHECK: smaxv {{h[0-9]+}}, [[V0]]
445 ; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
/external/capstone/suite/MC/AArch64/
Dneon-across.s.cs12 0x20,0xa8,0x30,0x0e = smaxv b0, v1.8b
13 0x20,0xa8,0x30,0x4e = smaxv b0, v1.16b
14 0x20,0xa8,0x70,0x0e = smaxv h0, v1.4h
15 0x20,0xa8,0x70,0x4e = smaxv h0, v1.8h
16 0x20,0xa8,0xb0,0x4e = smaxv s0, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-across.s33 smaxv b0, v1.8b
34 smaxv b0, v1.16b
35 smaxv h0, v1.4h
36 smaxv h0, v1.8h
37 smaxv s0, v1.4s
Dneon-diagnostics.s3773 smaxv s0, v1.2s
3795 smaxv d0, v1.2d define
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-across.s33 smaxv b0, v1.8b
34 smaxv b0, v1.16b
35 smaxv h0, v1.4h
36 smaxv h0, v1.8h
37 smaxv s0, v1.4s
Dneon-diagnostics.s3713 smaxv s0, v1.2s
3735 smaxv d0, v1.2d define
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dvector-reduce.ll187 ; CODE: smaxv b0, v0.8b
196 ; CODE: smaxv b0, v0.16b
205 ; CODE: smaxv h0, v0.4h
214 ; CODE: smaxv h0, v0.8h
223 ; CODE: smaxv s0, v0.4s
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1457 __ smaxv(b4, v5.V16B()); in GenerateTestSequenceNEON() local
1458 __ smaxv(b23, v0.V8B()); in GenerateTestSequenceNEON() local
1459 __ smaxv(h6, v0.V4H()); in GenerateTestSequenceNEON() local
1460 __ smaxv(h24, v8.V8H()); in GenerateTestSequenceNEON() local
1461 __ smaxv(s3, v16.V4S()); in GenerateTestSequenceNEON() local
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1221 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
1222 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
1223 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
1224 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
1225 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
Dlog-disasm1221 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
1222 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
1223 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
1224 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
1225 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
Dlog-cpufeatures-custom1220 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b ### {NEON} ###
1221 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b ### {NEON} ###
1222 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h ### {NEON} ###
1223 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h ### {NEON} ###
1224 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s ### {NEON} ###
Dlog-cpufeatures-colour1220 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b NEON
1221 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b NEON
1222 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h NEON
1223 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h NEON
1224 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s NEON
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc5233 { /* AArch64_SMAXVv16i8v, ARM64_INS_SMAXV: smaxv.16b $rd, $rn */
5237 { /* AArch64_SMAXVv4i16v, ARM64_INS_SMAXV: smaxv.4h $rd, $rn */
5241 { /* AArch64_SMAXVv4i32v, ARM64_INS_SMAXV: smaxv.4s $rd, $rn */
5245 { /* AArch64_SMAXVv8i16v, ARM64_INS_SMAXV: smaxv.8h $rd, $rn */
5249 { /* AArch64_SMAXVv8i8v, ARM64_INS_SMAXV: smaxv.8b $rd, $rn */
/external/vixl/src/aarch64/
Dsimulator-aarch64.h3460 LogicVRegister smaxv(VectorFormat vform,
4242 LogicVRegister smaxv(VectorFormat vform,

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