| /external/skqp/src/compute/skc/platforms/cl_12/kernels/ |
| D | place.cl | 194 skc_scatter_scan_max(__local union skc_subgroup_smem volatile * const smem,
209 // zero the volatile smem scratchpad using vector syntax
211 smem->scratch[get_sub_group_local_id()] = ( 0 );
217 smem->scratch[scratch_idx] = get_sub_group_local_id();
223 skc_int_v_t const scratch = smem->scratch[get_sub_group_local_id()];
258 skc_sk_to_ck(__local union skc_subgroup_smem volatile * const smem,
262 skc_uint const lo = smem->lo.sk[sk_idx]; // assumes prefix bit is 0
263 skc_uint const hi = smem->hi.sk[sk_idx];
280 skc_pk_to_ck(__local union skc_subgroup_smem volatile * const smem,
285 skc_uint const lo = smem->lo.pk[pk_idx] & SKC_TTXK_LO_MASK_ID_PREFIX; // assumes prefix bit is 1
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| D | rasterize.cl | 1081 __local struct skc_subgroup_smem volatile * const smem)
1090 if (smem->bin.aN.count[ii] > 0)
1092 skc_block_id_v_t const id = smem->bin.aN.id[ii];
1094 skc_uint const tts = smem->bin.aN.ttsb[ii][skc_subgroup_lane()];
1179 __local struct skc_subgroup_smem volatile * const smem,
1197 skc_uint ttsb_id_count = smem->pool.count; // scalar
1221 if (smem->bin.aN.count[winner] > 0)
1223 …skc_uint const elem_idx = smem->bin.aN.id[winner] * SKC_DEVICE_SUBBLOCK_WORDS + skc_subgroup_lane(…
1225 bp_elems[elem_idx].u32 = smem->bin.aN.ttsb[winner][skc_subgroup_lane()];
1250 ttsk_ryx[idx + ii] = skc_make_ttsk_ryx(smem,SKC_CMD_RASTERIZE_GET_COHORT(cmd),ii);
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| D | prefix.cl | 68 // smem accumulator
142 skc_accum_scatter(__local struct skc_subgroup_smem * const smem, skc_tts_v_t const tts_v)
171 SKC_ATOMIC_ADD_LOCAL_RELAXED_SUBGROUP(smem->accum.atomic.ttp + py C, dy C); \
184 smem->accum.aN.ttp[py C] = dy C;
199 skc_accum_flush(__local struct skc_subgroup_smem * const smem,
204 SKC_PREFIX_TTP_V const ttp_v = smem->accum.vN.ttp[get_sub_group_local_id()];
228 skc_accum_reset(__local struct skc_subgroup_smem * const smem)
231 smem->accum.zero.ttp[ii * SKC_PREFIX_SUBGROUP_SIZE + skc_subgroup_lane()] = ( 0 );
251 // SIMT without subgroup support can always emulate with smem
302 // SIMT without subgroup support can always emulate with smem
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| D | render.cl | 428 skc_tile_aa_zero(__local union skc_subgroup_smem * SKC_RESTRICT const smem)
458 smem->wide.area[ii][skc_subgroup_lane()] = ( 0 );
470 __local union skc_subgroup_smem * SKC_RESTRICT const smem,
510 smem->vN.area[0][skc_subgroup_lane()] += ttp_v << (SKC_SUBPIXEL_RESL_X_LOG2 + 1);
523 __local union skc_subgroup_smem * SKC_RESTRICT const smem,
586 smem->aN.area[SKC_TILE_HEIGHT + xy_idx C] += left C; \
587 smem->aN.area[ xy_idx C] += right C; \
597 SKC_ATOMIC_ADD_LOCAL_RELAXED_SUBGROUP(smem->atomic.area + \
600 SKC_ATOMIC_ADD_LOCAL_RELAXED_SUBGROUP(smem->atomic.area + xy_idx C, \
623 skc_tile_cover_nonzero(__local union skc_subgroup_smem * SKC_RESTRICT const smem,
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| /external/llvm-project/llvm/test/DebugInfo/X86/ |
| D | static_member_array.ll | 6 ; static int smem[];
10 ; int A::smem[] = { 0, 1, 2, 3 };
18 ; CHECK-NEXT: DW_AT_name {{.*}} "smem"
29 ; CHECK-NEXT: DW_AT_specification {{.*}}"smem"
58 !7 = !DIGlobalVariable(name: "smem", linkageName: "_ZN1A4smemE", scope: !2, file: !3, line: 8, type…
63 !12 = !DIDerivedType(tag: DW_TAG_member, name: "smem", scope: !13, file: !3, line: 4, baseType: !16…
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| /external/skqp/src/compute/hs/vk/ |
| D | hs_glsl_macros.h | 84 } smem
131 smem.m[smem_l_idx + (offset)]
134 smem.m[smem_r_idx + (offset)]
141 smem.m[gl_LocalInvocationID.x + (offset)]
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| /external/llvm-project/mlir/tools/mlir-cuda-runner/ |
| D | cuda-runtime-wrappers.cpp | 67 intptr_t blockZ, int32_t smem, CUstream stream, in mgpuLaunchKernel() argument
70 blockY, blockZ, smem, stream, params, in mgpuLaunchKernel()
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| /external/llvm-project/mlir/tools/mlir-rocm-runner/ |
| D | rocm-runtime-wrappers.cpp | 67 intptr_t blockZ, int32_t smem, in mgpuLaunchKernel() argument
71 blockX, blockY, blockZ, smem, in mgpuLaunchKernel()
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | concat_lib_gpu_impl.cu.cc | 73 GPU_DYNAMIC_SHARED_MEM_DECL(sizeof(T), unsigned char, smem); in concat_variable_kernel()
74 IntType* smem_col_scan = reinterpret_cast<IntType*>(smem); in concat_variable_kernel()
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| D | split_lib_gpu.cu.cc | 124 GPU_DYNAMIC_SHARED_MEM_DECL(sizeof(T), unsigned char, smem); in split_v_kernel()
125 IntType* smem_col_scan = reinterpret_cast<IntType*>(smem); in split_v_kernel()
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| D | reduction_gpu_kernels.cu.h | 556 value_type* const smem = reinterpret_cast<value_type*>(ss);
560 smem[local_plane * elems_per_plane + col] =
564 smem[local_plane * elems_per_plane + col] =
586 sum = op(smem[in_offset + local_plane * in_elems_per_plane + col],
587 smem[in_offset + local_plane * in_elems_per_plane +
590 sum = op(sum, smem[in_offset + local_plane * in_elems_per_plane +
593 smem[out_offset + local_plane * out_elems_per_plane + col] = sum;
606 smem[in_offset + local_plane * out_elems_per_plane + col];
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_optimizer.cpp | 1039 SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr.get()); in label_instruction() local
1042 bool prevent_overflow = smem->operands[0].size() > 2 || smem->prevent_overflow; in label_instruction()
1050 bool soe = smem->operands.size() >= (!smem->definitions.empty() ? 3 : 4); in label_instruction()
1052 (!ctx.info[smem->operands.back().tempId()].is_constant_or_literal(32) || in label_instruction()
1053 ctx.info[smem->operands.back().tempId()].val != 0)) { in label_instruction()
1057 smem->operands[1] = Operand(offset); in label_instruction()
1058 smem->operands.back() = Operand(base); in label_instruction()
1060 …w_instr = create_instruction<SMEM_instruction>(smem->opcode, Format::SMEM, smem->operands.size() +… in label_instruction()
1061 new_instr->operands[0] = smem->operands[0]; in label_instruction()
1063 if (smem->definitions.empty()) in label_instruction()
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| D | aco_print_ir.cpp | 338 const SMEM_instruction* smem = static_cast<const SMEM_instruction*>(instr); in print_instr_format_specific() local
339 if (smem->glc) in print_instr_format_specific()
341 if (smem->dlc) in print_instr_format_specific()
343 if (smem->nv) in print_instr_format_specific()
345 print_sync(smem->sync, output); in print_instr_format_specific()
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| D | aco_insert_waitcnt.cpp | 525 SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr); in kill() local
527 !smem->definitions.empty() && in kill()
528 !smem->sync.can_reorder()) { in kill()
787 SMEM_instruction *smem = static_cast<SMEM_instruction*>(instr); in gen() local
788 update_counters(ctx, event_smem, smem->sync); in gen()
793 !smem->sync.can_reorder()) in gen()
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| D | aco_assembler.cpp | 172 SMEM_instruction* smem = static_cast<SMEM_instruction*>(instr); in emit_instruction() local
199 assert(!smem->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
200 encoding |= smem->nv ? 1 << 15 : 0; in emit_instruction()
203 assert(!smem->nv); /* Non-volatile is not supported on GFX10 */ in emit_instruction()
204 encoding |= smem->dlc ? 1 << 14 : 0; in emit_instruction()
208 encoding |= smem->glc ? 1 << 16 : 0; in emit_instruction()
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| D | aco_instruction_selection.cpp | 3780 aco_opcode get_buffer_store_op(bool smem, unsigned bytes) in get_buffer_store_op() argument
3784 assert(!smem); in get_buffer_store_op()
3787 assert(!smem); in get_buffer_store_op()
3790 return smem ? aco_opcode::s_buffer_store_dword : aco_opcode::buffer_store_dword; in get_buffer_store_op()
3792 return smem ? aco_opcode::s_buffer_store_dwordx2 : aco_opcode::buffer_store_dwordx2; in get_buffer_store_op()
3794 assert(!smem); in get_buffer_store_op()
3797 return smem ? aco_opcode::s_buffer_store_dwordx4 : aco_opcode::buffer_store_dwordx4; in get_buffer_store_op()
3803 void split_buffer_store(isel_context *ctx, nir_intrinsic_instr *instr, bool smem, RegType dst_type, in split_buffer_store() argument
3831 if ((ctx->program->chip_class == GFX6 || smem) && byte == 12) in split_buffer_store()
4332 …Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_b… in visit_store_ls_or_es_output()
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | smem-no-clause-coalesced.mir | 4 # from the two adjacent smem instructions, because the first one has its
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| D | vccz-corrupt-bug-workaround.mir | 186 # of an outstanding smem load.
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| /external/mesa3d/src/panfrost/lib/ |
| D | decode.c | 370 struct pandecode_mapped_memory *smem = in pandecode_mfbd_bifrost_deps() local
373 const u16 *PANDECODE_PTR_VAR(samples, smem, params.sample_locations); in pandecode_mfbd_bifrost_deps()
938 … struct pandecode_mapped_memory *smem = pandecode_find_mapped_gpu_mem_containing(p->state); in pandecode_vertex_tiler_postfix_pre() local
939 uint32_t *cl = pandecode_fetch_gpu_mem(smem, p->state, MALI_RENDERER_STATE_LENGTH); in pandecode_vertex_tiler_postfix_pre()
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| /external/mesa3d/src/amd/compiler/tests/ |
| D | test_assembler.cpp | 37 bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0});
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| D | helpers.cpp | 138 bld.smem(aco_opcode::s_dcache_wb, false); in finish_program()
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| /external/mesa3d/docs/relnotes/ |
| D | 13.0.4.rst | 117 - radv: flush smem for uniform buffer bit.
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| /external/cpuinfo/test/dmesg/ |
| D | lg-k10-eu.log | 328 …-01 00:00:00.289] [50] bootmode_set_board_revision: board revision value is 9 and ntcode from smem
329 <6>[ 0.310773 / 01-01 00:00:00.289] [50] bootmode_set_lcd_maker_id: lcd maker id is 0 from smem
331 <6>[ 0.310811 / 01-01 00:00:00.289] [60] bootmode_set_cable: usb cable type is 8 from smem
332 <6>[ 0.310834 / 01-01 00:00:00.289] [70] bootmode_set_cable: usb port type is 1 from smem
478 …[ 0.312514 / 01-01 00:00:00.289] [780] bootmode_set_ddr_info: DDR Size info 1610612736 from smem
479 <6>[ 0.312536 / 01-01 00:00:00.289] [790] bootmode_set_ddr_info: DDR MR info 0x0 from smem
496 …1 00:00:00.289] [870] bootmode_set_ntcode: put ntcode is "1","FFF,FFF,FFFFFFFF,FFFFFFFF,11" to smem
497 … 0.312944 / 01-01 00:00:00.289] [880] bootmode_set_model_name: put lg_model_name LG-K420n to smem
501 <6>[ 0.313032 / 01-01 00:00:00.289] [900] bootmode_set_sim_num: put sim_num 1 to smem
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPU.td | 175 def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPU.td | 187 def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
|