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/external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/
Dsmlad11.ll4 ; A more complicated chain: 4 mul operations, so we expect 2 smlad calls.
13 ; CHECK: [[ACC:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V9]], i32 [[V11]], i32 %mac1{{\.}}054)
16 ; CHECK: [[V12:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V14]], i32 [[V16]], i32 [[ACC]])
18 ; And we don't want to see a 3rd smlad:
19 ; CHECK-NOT: call i32 @llvm.arm.smlad
21 ; CHECK: 2 arm-parallel-dsp - Number of smlad instructions generated
Dsmlad0.ll18 ; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V7]], i32 [[V5]], i32 %mac1{{\.}}026)
19 ; CHECK-NOT: call i32 @llvm.arm.smlad
21 ; CHECK-UNSUPPORTED-NOT: call i32 @llvm.arm.smlad
71 ; CHECK: [[V10]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac1{{\.}}058)
72 ; CHECK: [[V17]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac2{{\.}}057)
73 ; CHECK-NOT: call i32 @llvm.arm.smlad
137 ; CHECK-NOT: call i32 @llvm.arm.smlad
177 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dblocks.ll8 ; CHECK: call i32 @llvm.arm.smlad(i32 [[A]], i32 [[B]], i32 %acc)
60 ; CHECK: call i32 @llvm.arm.smlad(i32 [[A]], i32 [[B]], i32 0)
114 ; CHECK-NOT: call i32 @llvm.arm.smlad
140 ; CHECK: call i32 @llvm.arm.smlad
141 ; CHECK: call i32 @llvm.arm.smlad
142 ; CHECK: call i32 @llvm.arm.smlad
143 ; CHECK-NOT: call i32 @llvm.arm.smlad
216 ; CHECK-NOT: call i32 @llvm.arm.smlad
Doverlapping.ll10 ; CHECK: [[ACC:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc)
15 ; CHECK: [[RES:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A_1]], i32 [[LD_B_1]], i32 [[ACC]])
100 ; CHECK: [[RES:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 [[ACC2]])
136 ; CHECK: [[SMLAD:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc)
142 ; CHECK: [[RES:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A_2]], i32 [[LD_B_1]], i32 [[SMLAD]])
182 ; CHECK: [[SMLAD:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc)
Dinner-full-unroll.ll14 ; CHECK: [[SMLAD0:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[CIJ_LD]], i32 [[BIJ_LD]], i32 0)
21 ; CHECK: [[SMLAD1:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[CIJ_2_LD]], i32 [[BIJ_2_LD]], i32 [[SML…
100 ; CHECK: [[SMLAD0:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[CIJ_2_LD]], i32 [[BIJ_2_LD]], i32 [[ACC…
Dsmlad1.ll9 ; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V7]], i32 [[V5]], i32 %mac1{{\.}}026)
55 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dsmlaldx-2.ll20 ; CHECK-NOT: call i64 @llvm.arm.smlad
21 ; CHECK-UNSUPPORTED-NOT: call i64 @llvm.arm.smlad
203 ; CHECK-NOT: call i64 @llvm.arm.smlad
204 ; CHECK-UNSUPPORTED-NOT: call i64 @llvm.arm.smlad
Dsmlaldx-1.ll20 ; CHECK-NOT: call i64 @llvm.arm.smlad
21 ; CHECK-UNSUPPORTED-NOT: call i64 @llvm.arm.smlad
203 ; CHECK-NOT: call i64 @llvm.arm.smlad
204 ; CHECK-UNSUPPORTED-NOT: call i64 @llvm.arm.smlad
Dsmladx-1.ll22 ; CHECK-NOT: call i32 @llvm.arm.smlad
23 ; CHECK-UNSUPPORTED-NOT: call i32 @llvm.arm.smlad
148 ; CHECK-NOT: call i32 @llvm.arm.smlad
149 ; CHECK-UNSUPPORTED-NOT: call i32 @llvm.arm.smlad
Dsmlad9.ll6 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dsmlad10.ll6 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dsmlad5.ll5 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dexchange.ll112 ; CHECK: call i32 @llvm.arm.smlad(i32 [[LD_A_2]], i32 [[LD_B]], i32 [[X]])
228 ; CHECK: [[X:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc
269 ; CHECK-NOT: call i32 @llvm.arm.smlad
300 ; TODO: Would it be better to generate a smlad and then sign extend it?
348 ; CHECK: [[X:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 0
349 ; CHECK-NOT: call i32 @llvm.arm.smlad
Daliasing.ll7 ; CHECK-NOT: call i32 @llvm.arm.smlad
55 ; CHECK-NOT: call i32 @llvm.arm.smlad
108 ; CHECK: smlad
250 ; CHECK: smlad
454 ; TODO: I think we should be able to generate one smlad here. The search fails
457 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dsmlad12.ll5 ; CHECK: call i32 @llvm.arm.smlad
Dsmlad4.ll5 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dsmlad3.ll5 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dsmlad2.ll6 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dunroll-n-jam-smlad.ll6 ; CHECK-UNSUPPORTED-NOT: smlad r{{.}}
36 ; CHECK: smlad
37 ; CHECK: smlad
38 ; CHECK-NOT: smlad r{{.*}}
41 ; CHECK-REG-PRESSURE-NOT: call i32 @llvm.arm.smlad
Dsmlad8.ll7 ; CHECK-NOT: call i32 @llvm.arm.smlad
Dmulti-use-loads.ll23 ; CHECK-LE-NEXT: smlad r12, r4, lr, r12
125 ; CHECK-LE-NEXT: smlad r12, r4, r2, r12
228 ; CHECK-LE-NEXT: smlad r12, r4, lr, r12
331 ; CHECK-LE-NEXT: smlad r12, r4, r2, r12
435 ; CHECK-LE-NEXT: smlad lr, r4, r1, lr
Dsmlald2.ll143 ; CHECK-NOT: call i32 @llvm.arm.smlad
186 ; CHECK-NOT: call i32 @llvm.arm.smlad
/external/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dpitch_filter_armv6.S78 smlad r2, r11, r5, r2
84 smlad r2, r10, r4, r2
87 smlad r2, r11, r5, r2
112 smlad r2, r4, r7, r2
113 smlad r2, r5, r10, r2
/external/llvm-project/llvm/test/Transforms/HardwareLoops/ARM/
Dcalls-codegen.ll25 %res = call i32 @llvm.arm.smlad(i32 %load.a, i32 %load.b, i32 %acc)
60 declare i32 @llvm.arm.smlad(i32, i32, i32)
/external/llvm-project/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll340 define i32 @smlad(i32 %a, i32 %b, i32 %c) nounwind {
341 ; CHECK-LABEL: smlad
342 ; CHECK: smlad r0, r0, r1, r2
343 %tmp = call i32 @llvm.arm.smlad(i32 %a, i32 %b, i32 %c)
470 declare i32 @llvm.arm.smlad(i32, i32, i32) nounwind

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