| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 56 ; CHECK: smlawb r2, r0, r1, r2
62 %acc5 = call i32 @llvm.arm.smlawb(i32 %a, i32 %b, i32 %acc4)
107 declare i32 @llvm.arm.smlawb(i32, i32, i32) nounwind
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| D | smul.ll | 77 ; CHECK: smlawb r0, r0, r1, r2
78 ; DISABLED-NOT: smlawb
93 ; CHECK: smlawb r0, r0, r1, r2
94 ; DISABLED-NOT: smlawb
301 ; CHECK: smlawb r0, r0, r2, r1
302 ; DISABLED-NOT: smlawb
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| /external/llvm/test/CodeGen/ARM/ |
| D | smul.ll | 70 ; CHECK: smlawb
84 ; CHECK: smlawb
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| /external/arm-neon-tests/ |
| D | ref_dsp.c | 409 sres = smlawb(svar1, svar2, sacc); in exec_dsp()
416 sres = smlawb(svar1, svar2, sacc); in exec_dsp()
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| D | ref-rvct-all.txt | 8038 smlawb(0x12345678, 0x12345678, 0x1020304) = 0x7282098
8040 smlawb(0xf123f456, 0xf123f456, 0x1020304) = 0x1af55a4
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 272 smlawb r0, r1, r2, r3 label
703 # CHECK-NEXT: 1 2 1.00 smlawb r0, r1, r2, r3
1143 … - - - 1.00 - - - - - - - smlawb r0, r1, r2, r3
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| D | m4-int.s | 280 smlawb r0, r1, r2, r3 label
726 # CHECK-NEXT: 1 1 1.00 smlawb r0, r1, r2, r3
1164 # CHECK-NEXT: 1.00 smlawb r0, r1, r2, r3
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| D | cortex-a57-basic-instructions.s | 596 smlawb r2, r3, r10, r8
1466 # CHECK-NEXT: 1 3 1.00 smlawb r2, r3, r10, r8
2343 # CHECK-NEXT: - - - - 1.00 - - - smlawb r2, r3, r10, r8
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| D | cortex-a57-thumb.s | 622 smlawb r2, r3, r10, r8
1530 # CHECK-NEXT: 1 3 1.00 smlawb r2, r3, r10, r8
2444 # CHECK-NEXT: - - - - 1.00 - - - smlawb r2, r3, r10, r8
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 744 0x33,0xfb,0x0a,0x82 = smlawb r2, r3, r10, r8
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| D | basic-arm-instructions.s.cs | 669 0x83,0x8a,0x22,0xe1 = smlawb r2, r3, r10, r8
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3135 void smlawb(
3137 void smlawb(Register rd, Register rn, Register rm, Register ra) { in smlawb() function
3138 smlawb(al, rd, rn, rm, ra); in smlawb()
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| D | disasm-aarch32.h | 1127 void smlawb(
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2479 smlawb r2, r3, r10, r8
2484 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x83,0x8a,0x22,0xe1]
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| D | basic-thumb2-instructions.s | 2564 smlawb r2, r3, r10, r8
2570 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x33,0xfb,0x0a,0x82]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2449 smlawb r2, r3, r10, r8
2454 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x83,0x8a,0x22,0xe1]
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| D | basic-thumb2-instructions.s | 2355 smlawb r2, r3, r10, r8
2361 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x33,0xfb,0x0a,0x82]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1657 # CHECK: smlawb r2, r3, r10, r8
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| D | thumb2.txt | 1838 # CHECK: smlawb r2, r3, r10, r8
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1838 # CHECK: smlawb r2, r3, r10, r8
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| D | basic-arm-instructions.txt | 1657 # CHECK: smlawb r2, r3, r10, r8
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 778 { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */
6004 { /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 778 { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */
6004 { /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3012 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3081 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
|