| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 57 ; CHECK: smlawt r0, r0, r1, r2
63 %acc6 = call i32 @llvm.arm.smlawt(i32 %a, i32 %b, i32 %acc5)
108 declare i32 @llvm.arm.smlawt(i32, i32, i32) nounwind
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| D | smul.ll | 106 ; CHECK: smlawt r0, r0, r1, r2
107 ; DISABLED-NOT: smlawt
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| /external/arm-neon-tests/ |
| D | ref_dsp.c | 411 sres = smlawt(svar1, svar2, sacc); in exec_dsp()
418 sres = smlawt(svar1, svar2, sacc); in exec_dsp()
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| D | ref-rvct-all.txt | 8039 smlawt(0x12345678, 0x12345678, 0x1020304) = 0x24d63ba
8041 smlawt(0xf123f456, 0xf123f456, 0X1020304) = 0x1dedf9d
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| /external/llvm/test/CodeGen/ARM/ |
| D | smul.ll | 96 ; CHECK: smlawt
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 273 smlawt r0, r1, r2, r3 label
704 # CHECK-NEXT: 1 2 1.00 smlawt r0, r1, r2, r3
1144 … - - - 1.00 - - - - - - - smlawt r0, r1, r2, r3
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| D | m4-int.s | 281 smlawt r0, r1, r2, r3 label
727 # CHECK-NEXT: 1 1 1.00 smlawt r0, r1, r2, r3
1165 # CHECK-NEXT: 1.00 smlawt r0, r1, r2, r3
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| D | cortex-a57-basic-instructions.s | 597 smlawt r8, r3, r5, r9
1467 # CHECK-NEXT: 1 3 1.00 smlawt r8, r3, r5, r9
2344 # CHECK-NEXT: - - - - 1.00 - - - smlawt r8, r3, r5, r9
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| D | cortex-a57-thumb.s | 623 smlawt r8, r3, r5, r9
1531 # CHECK-NEXT: 1 3 1.00 smlawt r8, r3, r5, r9
2445 # CHECK-NEXT: - - - - 1.00 - - - smlawt r8, r3, r5, r9
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 745 0x33,0xfb,0x15,0x98 = smlawt r8, r3, r5, r9
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| D | basic-arm-instructions.s.cs | 670 0xc3,0x95,0x28,0xe1 = smlawt r8, r3, r5, r9
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3141 void smlawt(
3143 void smlawt(Register rd, Register rn, Register rm, Register ra) { in smlawt() function
3144 smlawt(al, rd, rn, rm, ra); in smlawt()
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| D | disasm-aarch32.h | 1130 void smlawt(
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2480 smlawt r8, r3, r5, r9
2485 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
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| D | basic-thumb2-instructions.s | 2565 smlawt r8, r3, r5, r9
2571 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2450 smlawt r8, r3, r5, r9
2455 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
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| D | basic-thumb2-instructions.s | 2356 smlawt r8, r3, r5, r9
2362 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1658 # CHECK: smlawt r8, r3, r5, r9
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| D | thumb2.txt | 1839 # CHECK: smlawt r8, r3, r5, r9
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1839 # CHECK: smlawt r8, r3, r5, r9
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| D | basic-arm-instructions.txt | 1658 # CHECK: smlawt r8, r3, r5, r9
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 781 { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */
6007 { /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 781 { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */
6007 { /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3014 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3083 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
|