| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 375 define i32 @smlsdx(i32 %a, i32 %b, i32 %c) nounwind {
376 ; CHECK-LABEL: smlsdx
377 ; CHECK: smlsdx r0, r0, r1, r2
378 %tmp = call i32 @llvm.arm.smlsdx(i32 %a, i32 %b, i32 %c)
475 declare i32 @llvm.arm.smlsdx(i32, i32, i32) nounwind
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| /external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/ |
| D | complex_dot_prod.ll | 4 ; TODO: Think we should be able to use smlsdx/smlsldx here.
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 275 smlsdx r0, r1, r2, r3 label
706 # CHECK-NEXT: 1 2 1.00 smlsdx r0, r1, r2, r3
1146 … - - - 1.00 - - - - - - - smlsdx r0, r1, r2, r3
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| D | m4-int.s | 283 smlsdx r0, r1, r2, r3 label
729 # CHECK-NEXT: 1 1 1.00 smlsdx r0, r1, r2, r3
1167 # CHECK-NEXT: 1.00 smlsdx r0, r1, r2, r3
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| D | cortex-a57-basic-instructions.s | 601 smlsdx r2, r3, r5, r8
1471 # CHECK-NEXT: 1 3 1.00 smlsdx r2, r3, r5, r8
2348 # CHECK-NEXT: - - - - 1.00 - - - smlsdx r2, r3, r5, r8
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| D | cortex-a57-thumb.s | 628 smlsdx r2, r3, r5, r8
1536 # CHECK-NEXT: 1 3 1.00 smlsdx r2, r3, r5, r8
2450 # CHECK-NEXT: - - - - 1.00 - - - smlsdx r2, r3, r5, r8
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 674 0x73,0x85,0x02,0xe7 = smlsdx r2, r3, r5, r8
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3153 void smlsdx(
3155 void smlsdx(Register rd, Register rn, Register rm, Register ra) { in smlsdx() function
3156 smlsdx(al, rd, rn, rm, ra); in smlsdx()
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| D | disasm-aarch32.h | 1136 void smlsdx(
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| D | disasm-aarch32.cc | 2679 void Disassembler::smlsdx( in smlsdx() function in vixl::aarch32::Disassembler
22008 smlsdx(CurrentCond(), in DecodeT32()
63894 smlsdx(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 10255 void Assembler::smlsdx( in smlsdx() function in vixl::aarch32::Assembler
10277 Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra); in smlsdx()
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2494 smlsdx r2, r3, r5, r8
2499 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 2581 smlsdx r2, r3, r5, r8
2587 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2464 smlsdx r2, r3, r5, r8
2469 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 2372 smlsdx r2, r3, r5, r8
2378 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1672 # CHECK: smlsdx r2, r3, r5, r8
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| D | thumb2.txt | 1855 # CHECK: smlsdx r2, r3, r5, r8
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1855 # CHECK: smlsdx r2, r3, r5, r8
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| D | basic-arm-instructions.txt | 1672 # CHECK: smlsdx r2, r3, r5, r8
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 787 { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */
6013 { /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 787 { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */
6013 { /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2889 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3091 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3160 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9903 "awt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smmlar\005smmls"
11138 …{ 1219 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_Is…
11139 …{ 1219 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsAR…
|