| /external/llvm-project/llvm/test/MC/ARM/ |
| D | equal-rdhi-rdlo-diagnostics.s | 18 smlsld r1, r1, r3, r4
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| D | basic-arm-instructions.s | 2507 smlsld r2, r9, r5, r1
2512 @ CHECK: smlsld r2, r9, r5, r1 @ encoding: [0x55,0x21,0x49,0xe7]
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| D | basic-thumb2-instructions.s | 2596 smlsld r2, r9, r5, r1
2602 @ CHECK: smlsld r2, r9, r5, r1 @ encoding: [0xd5,0xfb,0xc1,0x29]
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 382 define i64 @smlsld(i32 %a, i32 %b, i64 %c) nounwind {
383 ; CHECK-LABEL: smlsld
384 ; CHECK: smlsld r2, r3, r0, r1
385 %tmp = call i64 @llvm.arm.smlsld(i32 %a, i32 %b, i64 %c)
476 declare i64 @llvm.arm.smlsld(i32, i32, i64) nounwind
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 276 smlsld r0, r1, r2, r3 label
707 # CHECK-NEXT: 1 2 1.00 smlsld r0, r1, r2, r3
1147 … - - - 1.00 - - - - - - - smlsld r0, r1, r2, r3
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| D | m4-int.s | 284 smlsld r0, r1, r2, r3 label
730 # CHECK-NEXT: 1 1 1.00 smlsld r0, r1, r2, r3
1168 # CHECK-NEXT: 1.00 smlsld r0, r1, r2, r3
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| D | cortex-a57-basic-instructions.s | 604 smlsld r2, r9, r5, r1
1474 # CHECK-NEXT: 2 4 2.00 smlsld r2, r9, r5, r1
2351 # CHECK-NEXT: - - - - 2.00 - - - smlsld r2, r9, r5, r1
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| D | cortex-a57-thumb.s | 632 smlsld r2, r9, r5, r1
1540 # CHECK-NEXT: 2 4 2.00 smlsld r2, r9, r5, r1
2454 # CHECK-NEXT: - - - - 2.00 - - - smlsld r2, r9, r5, r1
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 754 0xd5,0xfb,0xc1,0x29 = smlsld r2, r9, r5, r1
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| D | basic-arm-instructions.s.cs | 677 0x55,0x21,0x49,0xe7 = smlsld r2, r9, r5, r1
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3159 void smlsld(
3161 void smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { in smlsld() function
3162 smlsld(al, rdlo, rdhi, rn, rm); in smlsld()
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| D | disasm-aarch32.h | 1139 void smlsld(
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| D | disasm-aarch32.cc | 2686 void Disassembler::smlsld( in smlsld() function in vixl::aarch32::Disassembler
22579 smlsld(CurrentCond(), in DecodeT32()
64302 smlsld(condition, in DecodeA32()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2477 smlsld r2, r9, r5, r1
2482 @ CHECK: smlsld r2, r9, r5, r1 @ encoding: [0x55,0x21,0x49,0xe7]
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| D | basic-thumb2-instructions.s | 2387 smlsld r2, r9, r5, r1
2393 @ CHECK: smlsld r2, r9, r5, r1 @ encoding: [0xd5,0xfb,0xc1,0x29]
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1685 # CHECK: smlsld r2, r9, r5, r1
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| D | thumb2.txt | 1870 # CHECK: smlsld r2, r9, r5, r1
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1870 # CHECK: smlsld r2, r9, r5, r1
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| D | basic-arm-instructions.txt | 1685 # CHECK: smlsld r2, r9, r5, r1
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 790 { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */
6016 { /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld${p} $ra, $rd, $rn, $rm */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 790 { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */
6016 { /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld${p} $ra, $rd, $rn, $rm */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2901 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3104 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3173 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9903 "awt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smmlar\005smmls"
11140 …{ 1226 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__C…
11141 …{ 1226 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__Con…
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