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/external/llvm-project/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll396 define i32 @smuad(i32 %a, i32 %b) nounwind {
397 ; CHECK-LABEL: smuad
398 ; CHECK: smuad r0, r0, r1
399 %tmp = call i32 @llvm.arm.smuad(i32 %a, i32 %b)
478 declare i32 @llvm.arm.smuad(i32, i32) nounwind
/external/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dpitch_filter_armv6.S77 smuad r2, r10, r4
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc68 M(smuad) \
Dtest-assembler-cond-rd-rn-rm-a32.cc69 M(smuad) \
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s284 smuad r0, r1, r2 label
715 # CHECK-NEXT: 1 2 1.00 smuad r0, r1, r2
1155 …- - - - 1.00 - - - - - - - smuad r0, r1, r2
Dm4-int.s292 smuad r0, r1, r2 label
738 # CHECK-NEXT: 1 2 1.00 smuad r0, r1, r2
1176 # CHECK-NEXT: 1.00 smuad r0, r1, r2
Dcortex-a57-basic-instructions.s620 smuad r2, r3, r4
1490 # CHECK-NEXT: 1 3 1.00 smuad r2, r3, r4
2367 # CHECK-NEXT: - - - - 1.00 - - - smuad r2, r3, r4
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs693 0x13,0xf4,0x02,0xe7 = smuad r2, r3, r4
/external/vixl/src/aarch32/
Dassembler-aarch32.h3201 void smuad(Condition cond, Register rd, Register rn, Register rm);
3202 void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); } in smuad() function
Ddisasm-aarch32.h1161 void smuad(Condition cond, Register rd, Register rn, Register rm);
Ddisasm-aarch32.cc2754 void Disassembler::smuad(Condition cond, in smuad() function in vixl::aarch32::Disassembler
21887 smuad(CurrentCond(), in DecodeT32()
63762 smuad(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
Dassembler-aarch32.cc10482 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) { in smuad() function in vixl::aarch32::Assembler
10502 Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm); in smuad()
Dmacro-assembler-aarch32.h3939 smuad(cond, rd, rn, rm); in Smuad()
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2563 smuad r2, r3, r4
2568 @ CHECK: smuad r2, r3, r4 @ encoding: [0x13,0xf4,0x02,0xe7]
Dbasic-thumb2-instructions.s2660 smuad r2, r3, r4
2666 @ CHECK: smuad r2, r3, r4 @ encoding: [0x23,0xfb,0x04,0xf2]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2533 smuad r2, r3, r4
2538 @ CHECK: smuad r2, r3, r4 @ encoding: [0x13,0xf4,0x02,0xe7]
Dbasic-thumb2-instructions.s2451 smuad r2, r3, r4
2457 @ CHECK: smuad r2, r3, r4 @ encoding: [0x23,0xfb,0x04,0xf2]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1741 # CHECK: smuad r2, r3, r4
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1741 # CHECK: smuad r2, r3, r4
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc814 { /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
6040 { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc814 { /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
6040 { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2852 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td3074 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td3143 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9904 "\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006smulbt\005"
11156 …{ 1280 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_Has…
11157 …{ 1280 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, {…

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