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Searched refs:smulh (Results 1 – 25 of 54) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Dsmulh-diagnostics.s7 smulh z0.b, z1.h, z2.h label
12 smulh z0.h, z1.s, z2.s label
17 smulh z0.s, z1.d, z2.d label
22 smulh z0.d, z1.b, z2.b label
31 smulh z0.d, z1.d, z31.d label
37 smulh z0.d, z1.d, z31.d label
Dsmulh.s10 smulh z0.b, z1.b, z2.b label
16 smulh z0.h, z1.h, z2.h label
22 smulh z29.s, z30.s, z31.s label
28 smulh z31.d, z31.d, z31.d label
/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dsmulh.s10 smulh z0.b, p7/m, z0.b, z31.b label
16 smulh z0.h, p7/m, z0.h, z31.h label
22 smulh z0.s, p7/m, z0.s, z31.s label
28 smulh z0.d, p7/m, z0.d, z31.d label
44 smulh z0.d, p7/m, z0.d, z31.d label
56 smulh z0.d, p7/m, z0.d, z31.d label
Dsmulh-diagnostics.s7 smulh z0.b, p7/m, z1.b, z2.b label
16 smulh z0.b, p8/m, z0.b, z1.b label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-int-mul-pred.ll49 ; CHECK: smulh z0.b, p0/m, z0.b, z1.b
51 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %pg,
59 ; CHECK: smulh z0.h, p0/m, z0.h, z1.h
61 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %pg,
69 ; CHECK: smulh z0.s, p0/m, z0.s, z1.s
71 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %pg,
79 ; CHECK: smulh z0.d, p0/m, z0.d, z1.d
81 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %pg,
131 declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>…
132 declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>…
[all …]
Dsve2-int-mul.ll121 ; CHECK: smulh z0.b, z0.b, z1.b
124 …%res = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %sel, <vscale x …
132 ; CHECK: smulh z0.h, z0.h, z1.h
135 …%res = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %sel, <vscale x 8…
143 ; CHECK: smulh z0.s, z0.s, z1.s
146 …%res = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %sel, <vscale x 4…
154 ; CHECK: smulh z0.d, z0.d, z1.d
157 …%res = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %sel, <vscale x 2…
312 declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>…
313 declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>…
[all …]
Dsrem-vector-lkk.ll291 ; CHECK-NEXT: smulh x9, x8, x9
301 ; CHECK-NEXT: smulh x9, x12, x9
311 ; CHECK-NEXT: smulh x10, x11, x10
Darm64-mul.ll21 ; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Dsrem-lkk.ll141 ; CHECK-NEXT: smulh x8, x0, x8
Ddp-3source.ll82 ; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Darm64-xaluo.ll219 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
489 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
502 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
722 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-canonical-form.txt9 # CHECK: smulh x0, x0, x0
Darm64-arithmetic.txt443 # CHECK: smulh x1, x2, x3
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-canonical-form.txt9 # CHECK: smulh x0, x0, x0
Darm64-arithmetic.txt443 # CHECK: smulh x1, x2, x3
Dbasic-a64-instructions.txt1109 # and smulh have them).
1111 # CHECK: smulh x30, x29, x28
1112 # CHECK: smulh xzr, x27, x26
1210 # CHECK: smulh x30, x29, x28
1211 # CHECK: smulh xzr, x27, x26
1212 # CHECK: smulh x25, xzr, x24
1213 # CHECK: smulh x23, x22, xzr
/external/llvm/test/CodeGen/AArch64/
Darm64-mul.ll21 ; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Ddp-3source.ll82 ; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Darm64-xaluo.ll210 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
379 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
575 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s482 smulh x1, x2, x3
485 ; CHECK: smulh x1, x2, x3 ; encoding: [0x41,0x7c,0x43,0x9b]
Dbasic-a64-instructions.s1634 smulh x30, x29, x28
1635 smulh xzr, x27, x26
1636 smulh x25, xzr, x24
1637 smulh x23, x22, xzr
/external/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s482 smulh x1, x2, x3
485 ; CHECK: smulh x1, x2, x3 ; encoding: [0x41,0x7c,0x43,0x9b]
Dbasic-a64-instructions.s1651 smulh x30, x29, x28
1652 smulh xzr, x27, x26
1653 smulh x25, xzr, x24
1654 smulh x23, x22, xzr
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s490 smulh x30, x29, x28 label
491 smulh xzr, x27, x26 label
532 smulh x30, x29, x28 label
533 smulh x23, x22, xzr label
1807 # CHECK-NEXT: 1 4 1.00 smulh x30, x29, x28
1808 # CHECK-NEXT: 1 4 1.00 smulh xzr, x27, x26
1849 # CHECK-NEXT: 1 4 1.00 smulh x30, x29, x28
1850 # CHECK-NEXT: 1 4 1.00 smulh x23, x22, xzr
2990 … - - - - - - - - - 1.00 - smulh x30, x29, x28
2991 … - - - - - - - - - 1.00 - smulh xzr, x27, x26
[all …]
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs638 0xbe,0x7f,0x5c,0x9b = smulh x30, x29, x28
639 0x7f,0x7f,0x5a,0x9b = smulh xzr, x27, x26
640 0xf9,0x7f,0x58,0x9b = smulh x25, xzr, x24
641 0xd7,0x7e,0x5f,0x9b = smulh x23, x22, xzr

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