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/external/llvm-project/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll417 define i32 @smusdx(i32 %a, i32 %b) nounwind {
418 ; CHECK-LABEL: smusdx
419 ; CHECK: smusdx r0, r0, r1
420 %tmp = call i32 @llvm.arm.smusdx(i32 %a, i32 %b)
481 declare i32 @llvm.arm.smusdx(i32, i32) nounwind
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc77 M(smusdx) \
Dtest-assembler-cond-rd-rn-rm-a32.cc78 M(smusdx) \
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s294 smusdx r0, r1, r2 label
725 # CHECK-NEXT: 1 2 1.00 smusdx r0, r1, r2
1165 … - - - 1.00 - - - - - - - smusdx r0, r1, r2
Dm4-int.s302 smusdx r0, r1, r2 label
748 # CHECK-NEXT: 1 2 1.00 smusdx r0, r1, r2
1186 # CHECK-NEXT: 1.00 smusdx r0, r1, r2
Dcortex-a57-basic-instructions.s639 smusdx r3, r9, r2
1509 # CHECK-NEXT: 1 3 1.00 smusdx r3, r9, r2
2386 # CHECK-NEXT: - - - - 1.00 - - - smusdx r3, r9, r2
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs797 0x49,0xfb,0x12,0xf3 = smusdx r3, r9, r2
Dbasic-arm-instructions.s.cs712 0x79,0xf2,0x03,0xe7 = smusdx r3, r9, r2
/external/vixl/src/aarch32/
Dassembler-aarch32.h3240 void smusdx(Condition cond, Register rd, Register rn, Register rm);
3241 void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); } in smusdx() function
Ddisasm-aarch32.h1185 void smusdx(Condition cond, Register rd, Register rn, Register rm);
Ddisasm-aarch32.cc2885 void Disassembler::smusdx(Condition cond, in smusdx() function in vixl::aarch32::Disassembler
21992 smusdx(CurrentCond(), in DecodeT32()
63879 smusdx(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
Dassembler-aarch32.cc10734 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) { in smusdx() function in vixl::aarch32::Assembler
10754 Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm); in smusdx()
Dmacro-assembler-aarch32.h4104 smusdx(cond, rd, rn, rm); in Smusdx()
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2624 smusdx r3, r9, r2
2629 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x79,0xf2,0x03,0xe7]
Dbasic-thumb2-instructions.s2729 smusdx r3, r9, r2
2735 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x49,0xfb,0x12,0xf3]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2594 smusdx r3, r9, r2
2599 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x79,0xf2,0x03,0xe7]
Dbasic-thumb2-instructions.s2520 smusdx r3, r9, r2
2526 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x49,0xfb,0x12,0xf3]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1802 # CHECK: smusdx r3, r9, r2
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1802 # CHECK: smusdx r3, r9, r2
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc844 { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */
6070 { /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc844 { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */
6070 { /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2870 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td3077 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td3146 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9905 "smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smusdx\006sqr"
11177 …{ 1347 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_H…
11178 …{ 1347 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6,…

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