Searched refs:sqrshrl (Results 1 – 9 of 9) sorted by relevance
11 …timated cost of 1 for instruction: %t3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 undef, i32 un…18 …timated cost of 1 for instruction: %t3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 undef, i32 un…25 …timated cost of 1 for instruction: %t3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 undef, i32 un…31 %t3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 undef, i32 undef, i32 undef, i32 48)38 declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32)
61 ; CHECK-NEXT: sqrshrl r0, r1, #64, r267 %3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %2, i32 %1, i32 %shift, i32 64)77 declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32)82 ; CHECK-NEXT: sqrshrl r0, r1, #48, r288 %3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %2, i32 %1, i32 %shift, i32 48)
114 # CHECK: sqrshrl lr, r3, #64, r8 @ encoding: [0x5f,0xea,0x2d,0x83]116 sqrshrl lr, r3, #64, r8 label120 sqrshrl lr, r3, #32, r8 label
70 return sqrshrl(value, shift); in test_sqrshrl()
30 # CHECK: sqrshrl lr, r3, #64, r8 @ encoding: [0x5f,0xea,0x2d,0x83]34 # CHECK: sqrshrl lr, r3, #48, r8 @ encoding: [0x5f,0xea,0xad,0x83]
550 def MVE_SQRSHRL : MVE_ScalarShiftDRegRegWithSat<"sqrshrl", 0b1>;
590 def MVE_SQRSHRL : MVE_ScalarShiftDRegRegWithSat<"sqrshrl", 0b1>;
9906 "shr\007sqrshrl\005sqshl\006sqshll\005srsda\005srsdb\005srshr\006srshrl\005"11180 …{ 1361 /* sqrshrl */, ARM::MVE_SQRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSa…
1605 "llvm.arm.mve.sqrshrl",11738 1, // llvm.arm.mve.sqrshrl