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Searched refs:sqrshrnt (Results 1 – 7 of 7) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Dsqrshrnt-diagnostics.s3 sqrshrnt z30.b, z10.h, #0 label
8 sqrshrnt z18.b, z27.h, #9 label
13 sqrshrnt z26.h, z4.s, #0 label
18 sqrshrnt z25.h, z10.s, #17 label
23 sqrshrnt z17.s, z0.d, #0 label
28 sqrshrnt z0.s, z15.d, #33 label
37 sqrshrnt z0.b, z0.b, #1 label
42 sqrshrnt z0.h, z0.h, #1 label
47 sqrshrnt z0.s, z0.s, #1 label
52 sqrshrnt z0.d, z0.d, #1 label
[all …]
Dsqrshrnt.s10 sqrshrnt z0.b, z0.h, #1 label
16 sqrshrnt z31.b, z31.h, #8 label
22 sqrshrnt z0.h, z0.s, #1 label
28 sqrshrnt z31.h, z31.s, #16 label
34 sqrshrnt z0.s, z0.d, #1 label
40 sqrshrnt z31.s, z31.d, #32 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve2-intrinsics-binary-narrowing-shr.ll400 ; CHECK: sqrshrnt z0.b, z1.h, #8
402 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnt.nxv8i16(<vscale x 16 x i8> %a,
410 ; CHECK: sqrshrnt z0.h, z1.s, #12
412 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnt.nxv4i32(<vscale x 8 x i16> %a,
420 ; CHECK: sqrshrnt z0.s, z1.d, #28
422 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnt.nxv2i64(<vscale x 4 x i32> %a,
510 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16…
511 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32…
512 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64…
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1465 …defm SQRSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b101, "sqrshrnt", int_aarch64_sve_s…
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12573 "\007sqrshlr\007sqrshrn\010sqrshrn2\010sqrshrnb\010sqrshrnt\010sqrshrun\t"
17820 …{ 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg…
17821 …{ 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg…
17822 …{ 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg…
25193 …{ 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorSReg…
25194 …{ 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorDReg…
25195 …{ 4876 /* sqrshrnt */, AArch64::SQRSHRNT_ZZI_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorHReg…
37295 { 4876 /* sqrshrnt */, 1 /* 0 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
37296 { 4876 /* sqrshrnt */, 2 /* 1 */, MCK_SVEVectorSReg, AMFBS_HasSVE2 },
37297 { 4876 /* sqrshrnt */, 1 /* 0 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td2644 …defm SQRSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b101, "sqrshrnt", int_aarch64_sve_s…
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc754 "llvm.aarch64.sve.sqrshrnt",
10887 29, // llvm.aarch64.sve.sqrshrnt