| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 67 uint32_t src1_neg : 1; member
565 .neg = instr->src1_neg, in print_instr()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 97 bits<1> src1_neg;
100 let Word0{25} = src1_neg;
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| D | R600ExpandSpecialInstrs.cpp | 343 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg); in runOnMachineFunction()
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| D | VIInstrFormats.td | 202 let Inst{54} = src1_modifiers{0}; // src1_neg
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| D | R600Instructions.td | 111 let src1_neg = 0;
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
180 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
186 "$src1_neg$src1$src1_rel, "
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| D | R600InstrInfo.cpp | 1327 OPERAND_CASE(AMDGPU::OpName::src1_neg) in getSlotedOps()
1366 AMDGPU::OpName::src1_neg, in buildSlotOfVectorInstruction()
1454 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_neg); in getFlagOp()
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| D | EvergreenInstructions.td | 409 let src1_neg = 0;
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 106 bits<1> src1_neg;
109 let Word0{25} = src1_neg;
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| D | R600ExpandSpecialInstrs.cpp | 279 SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_neg); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1305 OPERAND_CASE(R600::OpName::src1_neg) in getSlotedOps()
1344 R600::OpName::src1_neg, in buildSlotOfVectorInstruction()
1428 FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg); in getFlagOp()
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| D | R600Instructions.td | 121 let src1_neg = 0;
150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
196 "$src1_neg$src1$src1_rel, "
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| D | VOPInstructions.td | 598 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
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| D | EvergreenInstructions.td | 594 let src1_neg = 0;
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| D | R600ISelLowering.cpp | 2278 TII->getOperandIdx(Opcode, R600::OpName::src1_neg), in PostISelFolding()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 106 bits<1> src1_neg;
109 let Word0{25} = src1_neg;
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| D | R600ExpandSpecialInstrs.cpp | 279 SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_neg); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1304 OPERAND_CASE(R600::OpName::src1_neg) in getSlotedOps()
1343 R600::OpName::src1_neg, in buildSlotOfVectorInstruction()
1427 FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg); in getFlagOp()
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| D | R600Instructions.td | 121 let src1_neg = 0;
150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
196 "$src1_neg$src1$src1_rel, "
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| D | EvergreenInstructions.td | 483 let src1_neg = 0;
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| D | VOPInstructions.td | 588 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
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| D | R600ISelLowering.cpp | 2273 TII->getOperandIdx(Opcode, R600::OpName::src1_neg), in PostISelFolding()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | instr-a3xx.h | 455 uint32_t src1_neg : 1; /* negate */ member
519 uint32_t src1_neg : 1; member
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| D | ir3.c | 246 cat2->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)); in emit_cat2()
356 cat3->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)); in emit_cat3()
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| D | disasm-a3xx.c | 542 .neg = cat2->src1_neg, in print_instr_cat2()
611 .neg = cat3->src1_neg, in print_instr_cat3()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_optimize.c | 585 unsigned src1_neg = inst_add->U.I.SrcReg[1].Negate & dstmask; in peephole_add_presub_add() local
603 if (inst_add->U.I.SrcReg[1].Negate && src1_neg != dstmask) in peephole_add_presub_add()
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