Searched refs:src1_rel (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | EvergreenInstructions.td | 408 let src1_rel = 0;
471 let src1_rel = 0;
485 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
488 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
517 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
520 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
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| D | R600InstrFormats.td | 73 bits<1> src1_rel;
87 let Word0{22} = src1_rel;
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| D | R600Instructions.td | 110 let src1_rel = 0;
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
180 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
186 "$src1_neg$src1$src1_rel, "
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| D | R600InstrInfo.cpp | 1328 OPERAND_CASE(AMDGPU::OpName::src1_rel) in getSlotedOps()
1367 AMDGPU::OpName::src1_rel, in buildSlotOfVectorInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | EvergreenInstructions.td | 482 let src1_rel = 0;
540 let src1_rel = 0;
554 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
557 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
586 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
589 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
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| D | R600InstrFormats.td | 82 bits<1> src1_rel;
96 let Word0{22} = src1_rel;
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| D | R600Instructions.td | 120 let src1_rel = 0;
150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
196 "$src1_neg$src1$src1_rel, "
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| D | R600InstrInfo.cpp | 1305 OPERAND_CASE(R600::OpName::src1_rel) in getSlotedOps()
1344 R600::OpName::src1_rel, in buildSlotOfVectorInstruction()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | EvergreenInstructions.td | 593 let src1_rel = 0;
651 let src1_rel = 0;
665 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
668 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
697 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
700 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
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| D | R600InstrFormats.td | 82 bits<1> src1_rel;
96 let Word0{22} = src1_rel;
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| D | R600Instructions.td | 120 let src1_rel = 0;
150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
196 "$src1_neg$src1$src1_rel, "
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| D | R600InstrInfo.cpp | 1306 OPERAND_CASE(R600::OpName::src1_rel) in getSlotedOps()
1345 R600::OpName::src1_rel, in buildSlotOfVectorInstruction()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | instr-a3xx.h | 461 uint32_t src1_rel : 1; /* relative address */ member
525 uint32_t src1_rel : 1; member
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| D | ir3.c | 232 cat2->rel1.src1_rel = 1; in emit_cat2()
344 cat3->rel1.src1_rel = 1; in emit_cat3()
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| D | disasm-a3xx.c | 548 } else if (cat2->rel1.src1_rel) { in print_instr_cat2()
616 } else if (cat3->rel1.src1_rel) { in print_instr_cat3()
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