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Searched refs:src_flags (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/freedreno/ir3/
Dir3.c305 uint32_t src_flags = 0; in emit_cat3() local
316 src_flags |= IR3_REG_HALF; in emit_cat3()
323 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF)); in emit_cat3()
324 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF)); in emit_cat3()
325 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF)); in emit_cat3()
389 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF); in emit_cat3()
Dir3.h1456 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0; in ir3_COV() local
1458 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags); in ir3_COV()
/external/mesa3d/src/freedreno/vulkan/
Dtu_cmd_buffer.c2875 enum tu_cmd_access_mask src_flags = in tu_subpass_barrier() local
2881 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE; in tu_subpass_barrier()
2883 src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE; in tu_subpass_barrier()
2885 tu_flush_for_access(cache, src_flags, dst_flags); in tu_subpass_barrier()
3973 enum tu_cmd_access_mask src_flags = 0; in tu_barrier() local
3986 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE; in tu_barrier()
3997 src_flags |= vk2tu_access(srcAccessMask, gmem); in tu_barrier()
4002 tu_flush_for_access(cache, src_flags, dst_flags); in tu_barrier()
/external/mesa3d/src/intel/vulkan/
DgenX_cmd_buffer.c2378 VkAccessFlags src_flags = 0; in genX() local
2382 src_flags |= pMemoryBarriers[i].srcAccessMask; in genX()
2387 src_flags |= pBufferMemoryBarriers[i].srcAccessMask; in genX()
2392 src_flags |= pImageMemoryBarriers[i].srcAccessMask; in genX()
2442 anv_pipe_flush_bits_for_access_flags(cmd_buffer->device, src_flags) | in genX()
/external/mesa3d/src/amd/vulkan/
Dradv_cmd_buffer.c3187 VkAccessFlags src_flags, in radv_src_access_flush() argument
3201 for_each_bit(b, src_flags) { in radv_src_access_flush()