| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 123 src_reg shader_start_time;
170 const src_reg &src0);
172 const src_reg &src0, const src_reg &src1);
174 const src_reg &src0, const src_reg &src1,
175 const src_reg &src2);
181 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
182 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
183 …e EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg …
205 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
207 vec4_instruction *IF(src_reg src0, src_reg src1,
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| D | test_vec4_cmod_propagation.cpp | 147 src_reg src0 = src_reg(v, glsl_type::float_type); in TEST_F()
148 src_reg src1 = src_reg(v, glsl_type::float_type); in TEST_F()
149 src_reg zero(brw_imm_f(0.0f)); in TEST_F()
154 bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE); in TEST_F()
183 src_reg src0 = src_reg(v, glsl_type::float_type); in TEST_F()
184 src_reg src1 = src_reg(v, glsl_type::float_type); in TEST_F()
185 src_reg zero(brw_imm_f(0.0f)); in TEST_F()
189 bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE); in TEST_F()
220 src_reg src0 = src_reg(v, glsl_type::float_type); in TEST_F()
221 src_reg zero(brw_imm_f(0.0f)); in TEST_F()
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| D | brw_vec4_surface_builder.cpp | 34 static src_reg
35 emit_stride(const vec4_builder &bld, const src_reg &src, unsigned size, in emit_stride()
50 return src_reg(dst); in emit_stride()
60 static src_reg
61 emit_insert(const vec4_builder &bld, const src_reg &src, in emit_insert()
65 return src_reg(); in emit_insert()
76 return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1); in emit_insert()
91 src_reg
93 const src_reg &header, in emit_send()
94 const src_reg &addr, unsigned addr_sz, in emit_send()
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| D | brw_vec4_visitor.cpp | 32 const src_reg &src0, const src_reg &src1, in vec4_instruction()
33 const src_reg &src2) in vec4_instruction()
89 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, in emit()
90 const src_reg &src1, const src_reg &src2) in emit()
97 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, in emit()
98 const src_reg &src1) in emit()
104 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) in emit()
123 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
130 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
131 const src_reg &src1) \
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| D | brw_vec4_builder.h | 43 typedef brw::src_reg src_reg; typedef
245 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const in emit()
268 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, in emit()
269 const src_reg &src1) const in emit()
289 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, in emit()
290 const src_reg &src1, const src_reg &src2) const in emit()
335 emit_minmax(const dst_reg &dst, const src_reg &src0, in emit_minmax()
336 const src_reg &src1, brw_conditional_mod mod) const in emit_minmax()
347 src_reg
348 emit_uniformize(const src_reg &src) const in emit_uniformize()
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| D | brw_vec4_surface_builder.h | 32 src_reg
34 const src_reg &surface, const src_reg &addr,
39 emit_untyped_write(const vec4_builder &bld, const src_reg &surface,
40 const src_reg &addr, const src_reg &src,
44 src_reg
46 const src_reg &surface, const src_reg &addr,
47 const src_reg &src0, const src_reg &src1,
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| D | test_vec4_register_coalesce.cpp | 129 src_reg something = src_reg(v, glsl_type::float_type); in TEST_F()
138 v->emit(v->MOV(m0, src_reg(temp))); in TEST_F()
148 src_reg something = src_reg(v, glsl_type::float_type); in TEST_F()
160 src_reg src = src_reg(temp); in TEST_F()
174 src_reg some_src_1 = src_reg(v, glsl_type::vec4_type); in TEST_F()
175 src_reg some_src_2 = src_reg(v, glsl_type::vec4_type); in TEST_F()
185 v->emit(v->MOV(m0, src_reg(temp))); in TEST_F()
195 src_reg some_src_1 = src_reg(v, glsl_type::vec4_type); in TEST_F()
196 src_reg some_src_2 = src_reg(v, glsl_type::vec4_type); in TEST_F()
204 v->emit(v->MOV(to, src_reg(temp))); in TEST_F()
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| D | brw_fs_builder.h | 43 typedef fs_reg src_reg; typedef
276 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const in emit()
298 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, in emit()
299 const src_reg &src1) const in emit()
320 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, in emit()
321 const src_reg &src1, const src_reg &src2) const in emit()
344 emit(enum opcode opcode, const dst_reg &dst, const src_reg srcs[], in emit()
389 emit_minmax(const dst_reg &dst, const src_reg &src0, in emit_minmax()
390 const src_reg &src1, brw_conditional_mod mod) const in emit_minmax()
404 src_reg
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| D | brw_ir_vec4.h | 34 class src_reg : public backend_reg
37 DECLARE_RALLOC_CXX_OPERATORS(src_reg)
41 src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
42 src_reg();
43 src_reg(struct ::brw_reg reg);
45 bool equals(const src_reg &r) const;
46 bool negative_equals(const src_reg &r) const;
48 src_reg(class vec4_visitor *v, const struct glsl_type *type);
49 src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
51 explicit src_reg(const dst_reg ®);
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| D | brw_vec4_nir.cpp | 101 src_reg condition = get_nir_src(if_stmt->condition, BRW_REGISTER_TYPE_D, 1); in nir_emit_if()
184 new(v->mem_ctx) src_reg(v->get_nir_src(*indirect, in dst_reg_for_nir_reg()
219 src_reg
236 src_reg reg_as_src = src_reg(reg); in get_nir_src()
241 src_reg
249 src_reg
256 src_reg
261 return nir_src_is_const(src) ? src_reg(brw_imm_d(nir_src_as_int(src))) : in get_nir_src_imm()
265 src_reg
276 return src_reg(); in get_indirect_offset()
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| D | gen6_gs_visitor.cpp | 64 this->vertex_output = src_reg(this, in emit_prolog()
68 this->vertex_output_offset = src_reg(this, glsl_type::uint_type); in emit_prolog()
82 this->temp = src_reg(this, glsl_type::uint_type); in emit_prolog()
90 this->first_vertex = src_reg(this, glsl_type::uint_type); in emit_prolog()
96 this->prim_count = src_reg(this, glsl_type::uint_type); in emit_prolog()
101 this->destination_indices = src_reg(this, glsl_type::uvec4_type); in emit_prolog()
103 this->sol_prim_written = src_reg(this, glsl_type::uint_type); in emit_prolog()
105 this->svbi = src_reg(this, glsl_type::uvec4_type); in emit_prolog()
107 this->max_svbi = src_reg(this, glsl_type::uvec4_type); in emit_prolog()
109 src_reg(retype(brw_vec1_grf(1, 4), BRW_REGISTER_TYPE_UD)))); in emit_prolog()
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| D | gen6_gs_visitor.h | 73 src_reg vertex_output;
74 src_reg vertex_output_offset;
75 src_reg temp;
76 src_reg first_vertex;
77 src_reg prim_count;
78 src_reg primitive_id;
81 src_reg sol_prim_written;
82 src_reg svbi;
83 src_reg max_svbi;
84 src_reg destination_indices;
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| D | brw_vec4_tes.cpp | 86 input_read_header = src_reg(this, glsl_type::uvec4_type); in emit_prolog()
129 src_reg(brw_vec8_grf(1, 0)))); in nir_emit_intrinsic()
134 swizzle(src_reg(ATTR, 1, glsl_type::vec4_type), in nir_emit_intrinsic()
138 swizzle(src_reg(ATTR, 1, glsl_type::vec4_type), in nir_emit_intrinsic()
145 swizzle(src_reg(ATTR, 0, glsl_type::vec4_type), in nir_emit_intrinsic()
149 src_reg(ATTR, 1, glsl_type::float_type))); in nir_emit_intrinsic()
160 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic()
162 src_reg header = input_read_header; in nir_emit_intrinsic()
166 src_reg clamped_indirect_offset = src_reg(this, glsl_type::uvec4_type); in nir_emit_intrinsic()
176 header = src_reg(this, glsl_type::uvec4_type); in nir_emit_intrinsic()
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| D | test_vec4_dead_code_eliminate.cpp | 125 src_reg r1 = src_reg(v, glsl_type::vec4_type); in TEST_F()
126 src_reg r2 = src_reg(v, glsl_type::vec4_type); in TEST_F()
127 src_reg r3 = src_reg(v, glsl_type::vec4_type); in TEST_F()
128 src_reg r4 = src_reg(v, glsl_type::vec4_type); in TEST_F()
129 src_reg r5 = src_reg(v, glsl_type::vec4_type); in TEST_F()
130 src_reg r6 = src_reg(v, glsl_type::vec4_type); in TEST_F()
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| D | brw_vec4_tcs.cpp | 78 invocation_id = src_reg(this, glsl_type::uint_type); in emit_prolog()
119 emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); in emit_thread_end()
157 const src_reg &vertex_index, in emit_input_urb_read()
160 const src_reg &indirect_offset) in emit_input_urb_read()
173 inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header)); in emit_input_urb_read()
183 emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW))); in emit_input_urb_read()
185 src_reg src = src_reg(temp); in emit_input_urb_read()
195 const src_reg &indirect_offset) in emit_output_urb_read()
205 vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); in emit_output_urb_read()
213 emit(MOV(dst, swizzle(src_reg(read->dst), in emit_output_urb_read()
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| D | brw_vec4_tcs.h | 59 const src_reg &vertex_index,
62 const src_reg &indirect_offset);
66 const src_reg &indirect_offset);
68 void emit_urb_write(const src_reg &value, unsigned writemask,
69 unsigned base_offset, const src_reg &indirect_offset);
80 src_reg invocation_id;
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| /external/libaom/libaom/aom_dsp/x86/ |
| D | variance_impl_avx2.c | 52 #define MERGE_WITH_SRC(src_reg, reg) \ argument
53 exp_src_lo = _mm256_unpacklo_epi8(src_reg, reg); \
54 exp_src_hi = _mm256_unpackhi_epi8(src_reg, reg);
58 src_reg = _mm256_loadu_si256((__m256i const *)(src)); \
61 #define AVG_NEXT_SRC(src_reg, size_stride) \ argument
64 src_reg = _mm256_avg_epu8(src_reg, src_next_reg);
66 #define MERGE_NEXT_SRC(src_reg, size_stride) \ argument
68 MERGE_WITH_SRC(src_reg, src_next_reg)
110 src_reg = _mm256_inserti128_si256( \
117 #define AVG_NEXT_SRC_INSERT(src_reg, size_stride) \ argument
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| /external/iproute2/include/ |
| D | bpf_util.h | 74 .src_reg = SRC, \
82 .src_reg = SRC, \
92 .src_reg = 0, \
100 .src_reg = 0, \
110 .src_reg = SRC, \
118 .src_reg = SRC, \
128 .src_reg = 0, \
136 .src_reg = 0, \
148 .src_reg = SRC, \
154 .src_reg = 0, \
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_inline_literals.c | 111 struct rc_src_register * src_reg = in rc_inline_literals() local
114 if (src_reg->File != RC_FILE_CONSTANT) { in rc_inline_literals()
118 &c->Program.Constants.Constants[src_reg->Index]; in rc_inline_literals()
125 swz = GET_SWZ(src_reg->Swizzle, chan); in rc_inline_literals()
138 if (ret == -1 && src_reg->Abs) { in rc_inline_literals()
159 src_reg->File = RC_FILE_INLINE; in rc_inline_literals()
160 src_reg->Index = r300_float; in rc_inline_literals()
161 src_reg->Swizzle = new_swizzle; in rc_inline_literals()
162 src_reg->Negate = src_reg->Negate ^ negate_mask; in rc_inline_literals()
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| /external/bcc/src/cc/includes/ |
| D | libbpf.h | 131 .src_reg = SRC, \
139 .src_reg = SRC, \
149 .src_reg = 0, \
157 .src_reg = 0, \
167 .src_reg = SRC, \
177 .src_reg = 0, \
189 .src_reg = SRC, \
195 .src_reg = 0, \
212 .src_reg = 0, \
222 .src_reg = SRC, \
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| /external/bcc/src/cc/ |
| D | libbpf.h | 131 .src_reg = SRC, \
139 .src_reg = SRC, \
149 .src_reg = 0, \
157 .src_reg = 0, \
167 .src_reg = SRC, \
177 .src_reg = 0, \
189 .src_reg = SRC, \
195 .src_reg = 0, \
212 .src_reg = 0, \
222 .src_reg = SRC, \
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_cp.c | 313 struct ir3_register *src_reg = src->regs[1]; in reg_cp() local
321 reg->array = src_reg->array; in reg_cp()
324 reg->instr = ssa(src_reg); in reg_cp()
338 struct ir3_register *src_reg = src->regs[1]; in reg_cp() local
345 if (lower_immed(ctx, instr, n, src_reg, new_flags)) in reg_cp()
370 if (src_reg->flags & IR3_REG_CONST) { in reg_cp()
374 if ((src_reg->flags & IR3_REG_RELATIV) && in reg_cp()
383 (src_reg->flags & IR3_REG_RELATIV) && in reg_cp()
384 (src_reg->array.offset == 0)) in reg_cp()
398 src_reg = ir3_reg_clone(instr->block->shader, src_reg); in reg_cp()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| D | rc_test_helpers.c | 142 struct rc_src_register * src_reg = &inst->U.I.SrcReg[src_index]; in init_rc_normal_src() local
165 src_reg->Negate = RC_MASK_XYZW; in init_rc_normal_src()
170 src_reg->Abs = 1; in init_rc_normal_src()
175 src_reg->File = RC_FILE_TEMPORARY; in init_rc_normal_src()
177 src_reg->File = RC_FILE_INPUT; in init_rc_normal_src()
179 src_reg->File = RC_FILE_CONSTANT; in init_rc_normal_src()
181 src_reg->File = RC_FILE_NONE; in init_rc_normal_src()
186 src_reg->Index = strtol(tokens.Index.String, NULL, 10); in init_rc_normal_src()
194 src_reg->Swizzle = RC_SWIZZLE_XYZW; in init_rc_normal_src()
197 src_reg->Swizzle = RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_UNUSED); in init_rc_normal_src()
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| /external/mesa3d/src/mesa/program/ |
| D | ir_to_mesa.cpp | 62 class src_reg;
69 class src_reg { class
71 src_reg(gl_register_file file, int index, const glsl_type *type) in src_reg() function in __anon83d07f0a0111::src_reg
83 src_reg() in src_reg() function in __anon83d07f0a0111::src_reg
92 explicit src_reg(dst_reg reg);
99 src_reg *reladdr;
120 explicit dst_reg(src_reg reg);
126 src_reg *reladdr;
131 src_reg::src_reg(dst_reg reg) in src_reg() function in src_reg
140 dst_reg::dst_reg(src_reg reg) in dst_reg()
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| /external/libvpx/libvpx/vpx_dsp/x86/ |
| D | vpx_subpixel_4t_intrin_sse2.c | 31 __m128i src_reg, src_reg_shift_1, src_reg_shift_2, src_reg_shift_3; in vpx_filter_block1d16_h4_sse2() local
55 src_reg = _mm_loadu_si128((const __m128i *)src_ptr); in vpx_filter_block1d16_h4_sse2()
56 src_reg_shift_1 = _mm_srli_si128(src_reg, 1); in vpx_filter_block1d16_h4_sse2()
57 src_reg_shift_2 = _mm_srli_si128(src_reg, 2); in vpx_filter_block1d16_h4_sse2()
58 src_reg_shift_3 = _mm_srli_si128(src_reg, 3); in vpx_filter_block1d16_h4_sse2()
61 even = mm_madd_add_epi8_sse2(&src_reg, &src_reg_shift_2, &kernel_reg_23, in vpx_filter_block1d16_h4_sse2()
72 src_reg = _mm_loadu_si128((const __m128i *)(src_ptr + 8)); in vpx_filter_block1d16_h4_sse2()
73 src_reg_shift_1 = _mm_srli_si128(src_reg, 1); in vpx_filter_block1d16_h4_sse2()
74 src_reg_shift_2 = _mm_srli_si128(src_reg, 2); in vpx_filter_block1d16_h4_sse2()
75 src_reg_shift_3 = _mm_srli_si128(src_reg, 3); in vpx_filter_block1d16_h4_sse2()
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