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Searched refs:srlv (Results 1 – 25 of 131) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dlshr.ll98 ; MIPS2-NEXT: srlv $2, $4, $5
103 ; MIPS32-NEXT: srlv $2, $4, $5
108 ; MIPS32R2-NEXT: srlv $2, $4, $5
113 ; MIPS32R6-NEXT: srlv $2, $4, $5
118 ; MIPS3-NEXT: srlv $2, $4, $5
123 ; MIPS4-NEXT: srlv $2, $4, $5
128 ; MIPS64-NEXT: srlv $2, $4, $5
133 ; MIPS64R2-NEXT: srlv $2, $4, $5
138 ; MIPS64R6-NEXT: srlv $2, $4, $5
143 ; MMR3-NEXT: srlv $2, $4, $5
[all …]
Dashr.ll282 ; MIPS-NEXT: srlv $1, $5, $7
296 ; MIPS32-NEXT: srlv $1, $5, $7
310 ; 32R2-NEXT: srlv $1, $5, $7
330 ; 32R6-NEXT: srlv $5, $5, $7
362 ; MMR3-NEXT: srlv $2, $5, $7
382 ; MMR6-NEXT: srlv $5, $5, $7
413 ; MIPS-NEXT: srlv $14, $6, $2
416 ; MIPS-NEXT: srlv $11, $7, $2
431 ; MIPS-NEXT: srlv $9, $10, $9
441 ; MIPS-NEXT: srlv $1, $5, $24
[all …]
Dshl.ll348 ; MIPS2-NEXT: srlv $2, $3, $2
361 ; MIPS32-NEXT: srlv $2, $3, $2
374 ; MIPS32R2-NEXT: srlv $2, $3, $2
387 ; MIPS32R6-NEXT: srlv $2, $3, $2
427 ; MMR3-NEXT: srlv $2, $4, $2
441 ; MMR6-NEXT: srlv $2, $3, $2
468 ; MIPS2-NEXT: srlv $9, $6, $3
473 ; MIPS2-NEXT: srlv $1, $7, $3
492 ; MIPS2-NEXT: srlv $11, $11, $13
504 ; MIPS2-NEXT: srlv $14, $24, $14
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s15 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
20 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
23 # CHECK-EL: srlv $2, $2, $3 # encoding: [0x43,0x00,0x50,0x10]
35 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
40 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
43 # CHECK-EB: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
52 srlv $2, $3, $5
Drotations32.s11 # CHECK-32: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
18 # CHECK-32: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
53 # CHECK-32: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
59 # CHECK-32: srlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x06]
Drotations64.s11 # CHECK-64: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
18 # CHECK-64: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
53 # CHECK-64: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
59 # CHECK-64: srlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x06]
Dmips64-alu-instructions.s29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
57 srlv $2, $3, $5
Dmips-alu-instructions.s31 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
62 srlv $2, $3, $5
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s15 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
20 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
23 # CHECK-EL: srlv $2, $2, $3 # encoding: [0x43,0x00,0x50,0x10]
35 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
40 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
43 # CHECK-EB: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
52 srlv $2, $3, $5
Drotations32.s11 # CHECK-32: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
18 # CHECK-32: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
53 # CHECK-32: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
59 # CHECK-32: srlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x06]
Drotations64.s11 # CHECK-64: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
18 # CHECK-64: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
53 # CHECK-64: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
59 # CHECK-64: srlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x06]
Dmips64-alu-instructions.s29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
57 srlv $2, $3, $5
Dmips-alu-instructions.s31 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
62 srlv $2, $3, $5
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfunnel-shift-rot.ll55 ; CHECK-NEXT: srlv $2, $3, $2
69 ; CHECK-NEXT: srlv $2, $4, $2
81 ; CHECK-BE-NEXT: srlv $6, $4, $3
89 ; CHECK-BE-NEXT: srlv $10, $10, $11
95 ; CHECK-BE-NEXT: srlv $5, $5, $3
109 ; CHECK-LE-NEXT: srlv $7, $5, $2
117 ; CHECK-LE-NEXT: srlv $10, $10, $11
123 ; CHECK-LE-NEXT: srlv $4, $4, $2
151 ; CHECK-NEXT: srlv $6, $6, $2
153 ; CHECK-NEXT: srlv $5, $5, $8
[all …]
Dfunnel-shift.ll41 ; CHECK-NEXT: srlv $2, $2, $3
79 ; CHECK-BE-NEXT: srlv $4, $5, $4
85 ; CHECK-BE-NEXT: srlv $9, $8, $5
99 ; CHECK-BE-NEXT: srlv $3, $3, $5
142 ; CHECK-LE-NEXT: srlv $4, $5, $4
148 ; CHECK-LE-NEXT: srlv $9, $8, $5
162 ; CHECK-LE-NEXT: srlv $2, $2, $5
294 ; CHECK-NEXT: srlv $2, $1, $2
303 ; CHECK-NEXT: srlv $1, $5, $1
348 ; CHECK-BE-NEXT: srlv $6, $6, $2
[all …]
Datomic-min-max.ll857 ; MIPS-NEXT: srlv $1, $1, $10
897 ; MIPSR6-NEXT: srlv $1, $1, $10
935 ; MM-NEXT: srlv $1, $1, $10
974 ; MMR6-NEXT: srlv $1, $1, $10
1014 ; MIPSEL-NEXT: srlv $1, $1, $10
1055 ; MIPSELR6-NEXT: srlv $1, $1, $10
1094 ; MMEL-NEXT: srlv $1, $1, $10
1134 ; MMELR6-NEXT: srlv $1, $1, $10
1173 ; MIPS64-NEXT: srlv $1, $1, $10
1213 ; MIPS64R6-NEXT: srlv $1, $1, $10
[all …]
Datomic.ll2267 ; MIPS32-NEXT: srlv $1, $1, $3
2302 ; MIPS32O0-NEXT: srlv $1, $1, $9
2341 ; MIPS32R2-NEXT: srlv $1, $1, $3
2372 ; MIPS32R6-NEXT: srlv $1, $1, $3
2405 ; MIPS32R6O0-NEXT: srlv $1, $1, $9
2441 ; MIPS4-NEXT: srlv $1, $1, $3
2475 ; MIPS64-NEXT: srlv $1, $1, $3
2509 ; MIPS64R2-NEXT: srlv $1, $1, $3
2540 ; MIPS64R6-NEXT: srlv $1, $1, $3
2574 ; MIPS64R6O0-NEXT: srlv $1, $1, $9
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dlshr.ll46 ; ALL: srlv $[[T0:[0-9]+]], $4, $5
59 ; ALL: srlv $[[T0:[0-9]+]], $4, $5
72 ; ALL: srlv $2, $4, $5
82 ; M2: srlv $[[T0:[0-9]+]], $4, $7
86 ; M2: srlv $[[T2:[0-9]+]], $5, $7
99 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
104 ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
110 ; 32R6: srlv $[[T0:[0-9]+]], $5, $7
117 ; 32R6: srlv $[[T7:[0-9]+]], $4, $7
125 ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
[all …]
Dashr.ll88 ; M2: srlv $[[T2:[0-9]+]], $5, $7
101 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
119 ; 32R6: srlv $[[T6:[0-9]+]], $5, $7
131 ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
148 ; MMR6: srlv $[[T6:[0-9]+]], $5, $7
Dshl.ll105 ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
118 ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
129 ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
144 ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
155 ; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dbitwise.ll298 ; MIPS32-NEXT: srlv $2, $4, $5
340 ; MIPS32-NEXT: srlv $2, $1, $2
360 ; MIPS32-NEXT: srlv $4, $3, $4
392 ; MIPS32-NEXT: srlv $3, $5, $3
426 ; MIPS32-NEXT: srlv $1, $2, $7
427 ; MIPS32-NEXT: srlv $7, $5, $7
430 ; MIPS32-NEXT: srlv $2, $2, $8
/external/google-breakpad/src/common/android/include/asm-mips/
Dasm.h126 #define INT_SRLV srlv
166 #define LONG_SRLV srlv
218 #define PTR_SRLV srlv
/external/capstone/suite/MC/Mips/
Dmicromips-shift-instructions.s.cs7 0x65,0x00,0x50,0x10 = srlv $v0, $v1, $a1
Dmicromips-shift-instructions-EB.s.cs7 0x00,0x65,0x10,0x50 = srlv $v0, $v1, $a1
/external/llvm/test/CodeGen/Mips/
Datomic.ll160 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
205 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
251 ; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]]
291 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
340 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
384 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
442 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
478 ; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $

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