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Searched refs:ssat (Results 1 – 25 of 69) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/
Dssat.ll20 ; V6T2: ssat r0, #24, r0
21 ; V4T-NOT: ssat
34 ; V6T2: ssat r0, #12, r0
35 ; V4T-NOT: ssat
48 ; V6T2: ssat r0, #6, r0
49 ; V4T-NOT: ssat
67 ; V6T2: ssat r0, #24, r0
68 ; V4T-NOT: ssat
80 ; V6T2: ssat r0, #24, r0
81 ; V4T-NOT: ssat
[all …]
Dssat-with-shift.ll8 ; CHECK-NEXT: ssat r0, #8, r0, lsl #7
12 %0 = tail call i32 @llvm.arm.ssat(i32 %shl, i32 8)
19 ; CHECK-NEXT: ssat r0, #8, r0, asr #7
23 %0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8)
30 ; CHECK-NEXT: ssat r0, #16, r0, lsl #15
44 ; CHECK-NEXT: ssat r0, #16, r0, asr #15
55 declare i32 @llvm.arm.ssat(i32, i32)
Dssat-v4t.ll3 ; CHECK: Cannot select: intrinsic %llvm.arm.ssat
4 define i32 @ssat() nounwind {
5 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
9 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
Dssat-lower.ll5 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
7 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 0)
11 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
Dssat-upper.ll5 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
7 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 33)
11 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
Dssat-unroll-loops.ll21 ; CHECK-NEXT: ssat r3, #16, r3, asr #14
33 ; CHECK-NEXT: ssat r12, #16, r12, asr #14
40 ; CHECK-NEXT: ssat r12, #16, r12, asr #14
Dacle-intrinsics.ll12 ; CHECK: ssat r0, #32, r0
13 %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 32)
20 ; CHECK: ssat r0, #1, r0
21 %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 1)
423 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
/external/llvm/test/CodeGen/ARM/
Dssat.ll19 ; CHECK: ssat r0, #24, r0
32 ; CHECK: ssat r0, #12, r0
45 ; CHECK: ssat r0, #6, r0
63 ; CHECK: ssat r0, #24, r0
75 ; CHECK: ssat r0, #24, r0
87 ; CHECK: ssat r0, #24, r0
99 ; CHECK: ssat r0, #24, r0
111 ; CHECK: ssat r0, #24, r0
128 ; CHECK: ssat r0, #24, r0
146 ; CHECK-NOT: ssat
[all …]
Dssat-lower.ll5 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
7 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 0)
11 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
Dssat-upper.ll5 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
7 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 33)
11 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
Dsat-arith.ll28 ; CHECK: ssat [[R1:.*]], #32, [[R0]]
29 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 32)
37 ; CHECK: ssat [[R1:.*]], #1, [[R0]]
38 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
62 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
/external/llvm/test/MC/ARM/
Ddiagnostics.s235 ssat r8, #0, r10, lsl #8
236 ssat r8, #33, r10, lsl #8
237 ssat r8, #1, r10, lsl #-1
238 ssat r8, #1, r10, lsl #32
239 ssat r8, #1, r10, asr #0
240 ssat r8, #1, r10, asr #33
241 ssat r8, #1, r10, lsr #5
242 ssat r8, #1, r10, lsl fred
243 ssat r8, #1, r10, lsl #fred
246 @ CHECK-ERRORS: ssat r8, #0, r10, lsl #8
[all …]
Dthumb2-diagnostics.s94 ssat r0, #1, r0, asr #32
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dtarget-intrinsics.ll9 …l: Found an estimated cost of 1 for instruction: %t1 = call i32 @llvm.arm.ssat(i32 undef, i32 unde…
16 …l: Found an estimated cost of 1 for instruction: %t1 = call i32 @llvm.arm.ssat(i32 undef, i32 unde…
23 …l: Found an estimated cost of 1 for instruction: %t1 = call i32 @llvm.arm.ssat(i32 undef, i32 unde…
29 %t1 = call i32 @llvm.arm.ssat(i32 undef, i32 undef)
36 declare i32 @llvm.arm.ssat(i32, i32)
/external/webrtc/common_audio/signal_processing/
Dfilter_ar_fast_q12_armv7.S89 ssat r7, #16, r6, asr #12
92 ssat r6, #16, r6, asr #12
100 ssat r7, #16, r6, asr #12
103 ssat r6, #16, r6, asr #12
/external/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dpitch_filter_armv6.S93 ssat r7, #16, r4, asr #13
120 ssat r10, #16, r10, asr #14
129 ssat r2, #16, r4
133 ssat r2, #16, r2
Dlattice_armv7.S63 ssat r11, #16, r11, asr #15
64 ssat r5, #16, r10, asr #15
/external/llvm-project/llvm/test/MC/ARM/
Ddiagnostics.s263 ssat r8, #0, r10, lsl #8
264 ssat r8, #33, r10, lsl #8
265 ssat r8, #1, r10, lsl #-1
266 ssat r8, #1, r10, lsl #32
267 ssat r8, #1, r10, asr #0
268 ssat r8, #1, r10, asr #33
269 ssat r8, #1, r10, lsr #5
270 ssat r8, #1, r10, lsl fred
271 ssat r8, #1, r10, lsl #fred
274 @ CHECK-ERRORS: ssat r8, #0, r10, lsl #8
[all …]
/external/libhevc/decoder/arm/
Dihevcd_itrans_recon_dc_luma.s71 ssat r8,#16,r8,asr #7
73 ssat r6,#16,r5,asr #12
Dihevcd_itrans_recon_dc_chroma.s70 ssat r8,#16,r8,asr #7
72 ssat r6,#16,r5,asr #12
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt77 # CHECK-NOT: ssat r0, #17, r12, lsl #0
78 # CHECK: ssat r0, #17, r12
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt77 # CHECK-NOT: ssat r0, #17, r12, lsl #0
78 # CHECK: ssat r0, #17, r12
/external/mesa3d/src/compiler/glsl/
Dlower_blend_equation_advanced.cpp253 ir_rvalue *ssat = satv3(csat); in set_lum_sat() local
264 assign(color, div(mul(sub(cbase, minbase), ssat), sbase)), in set_lum_sat()
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs751 0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10
752 0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10
753 0x9a,0x8f,0xa0,0xe6 = ssat r8, #1, r10, lsl #31
754 0x5a,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #32
755 0xda,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #1
Dbasic-thumb2-instructions.s.cs821 0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10
822 0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10
823 0x0a,0xf3,0xc0,0x78 = ssat r8, #1, r10, lsl #31
824 0x2a,0xf3,0x40,0x08 = ssat r8, #1, r10, asr #1

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