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Searched refs:sshl (Results 1 – 25 of 62) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/
Dneon-shift.s9 sshl v0.8b, v1.8b, v2.8b
10 sshl v0.16b, v1.16b, v2.16b
11 sshl v0.4h, v1.4h, v2.4h
12 sshl v0.8h, v1.8h, v2.8h
13 sshl v0.2s, v1.2s, v2.2s
14 sshl v0.4s, v1.4s, v2.4s
15 sshl v0.2d, v1.2d, v2.2d
Dneon-scalar-shift.s6 sshl d17, d31, d8
/external/llvm/test/MC/AArch64/
Dneon-shift.s9 sshl v0.8b, v1.8b, v2.8b
10 sshl v0.16b, v1.16b, v2.16b
11 sshl v0.4h, v1.4h, v2.4h
12 sshl v0.8h, v1.8h, v2.8h
13 sshl v0.2s, v1.2s, v2.2s
14 sshl v0.4s, v1.4s, v2.4s
15 sshl v0.2d, v1.2d, v2.2d
Dneon-scalar-shift.s6 sshl d17, d31, d8
/external/capstone/suite/MC/AArch64/
Dneon-shift.s.cs2 0x20,0x44,0x22,0x0e = sshl v0.8b, v1.8b, v2.8b
3 0x20,0x44,0x22,0x4e = sshl v0.16b, v1.16b, v2.16b
4 0x20,0x44,0x62,0x0e = sshl v0.4h, v1.4h, v2.4h
5 0x20,0x44,0x62,0x4e = sshl v0.8h, v1.8h, v2.8h
6 0x20,0x44,0xa2,0x0e = sshl v0.2s, v1.2s, v2.2s
7 0x20,0x44,0xa2,0x4e = sshl v0.4s, v1.4s, v2.4s
8 0x20,0x44,0xe2,0x4e = sshl v0.2d, v1.2d, v2.2d
Dneon-scalar-shift.s.cs2 0xf1,0x47,0xe8,0x5e = sshl d17, d31, d8
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s152 sshl v0.4s, v0.4s, v30.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
153 sshl v2.4s, v2.4s, v30.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
154 sshl v4.4s, v4.4s, v30.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
155 sshl v6.4s, v6.4s, v30.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
345 sshl v0.4s, v0.4s, v30.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
346 sshl v2.4s, v2.4s, v30.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
347 sshl v4.4s, v4.4s, v30.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
348 sshl v6.4s, v6.4s, v30.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
579 sshl v16.4s, v16.4s, v0.4s
580 sshl v17.4s, v17.4s, v0.4s
[all …]
Dih264_ihadamard_scaling_av8.s149 sshl v0.4s, v0.4s, v14.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
150 sshl v1.4s, v1.4s, v14.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
151 sshl v2.4s, v2.4s, v14.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
152 sshl v3.4s, v3.4s, v14.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
239 sshl v2.4s, v2.4s, v28.4s
240 sshl v3.4s, v3.4s, v28.4s
Dih264_resi_trans_quant_av8.s183 sshl v20.4s, v20.4s, v24.4s //shift row 1
184 sshl v21.4s, v21.4s, v24.4s //shift row 2
185 sshl v22.4s, v22.4s, v24.4s //shift row 3
186 sshl v23.4s, v23.4s, v24.4s //shift row 4
385 sshl v20.4s, v20.4s, v24.4s //shift row 1
386 sshl v21.4s, v21.4s, v24.4s //shift row 2
387 sshl v22.4s, v22.4s, v24.4s //shift row 3
388 sshl v23.4s, v23.4s, v24.4s //shift row 4
Dih264_iquant_itrans_recon_dc_av8.s142 sshl v0.4s, v0.4s, v30.4s
358 sshl v0.4s, v0.4s, v3.4s
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_planar.s209 sshl v27.8h, v27.8h, v29.8h //(1)shr
226 sshl v30.8h, v30.8h, v29.8h //(2)shr
243 sshl v28.8h, v28.8h, v29.8h //(3)shr
260 sshl v25.8h, v25.8h, v29.8h //(4)shr
276 sshl v16.8h, v16.8h, v29.8h //(5)shr
293 sshl v18.8h, v18.8h, v29.8h //(6)shr
309 sshl v26.8h, v26.8h, v29.8h //(7)shr
348 sshl v24.8h, v24.8h, v29.8h //(8)shr
382 sshl v27.8h, v27.8h, v29.8h //(1)shr
402 sshl v30.8h, v30.8h, v29.8h //(2)shr
[all …]
Dihevc_weighted_pred_uni.s183 sshl v4.4s,v4.4s,v28.4s
193 sshl v6.4s,v6.4s,v28.4s
199 sshl v7.4s,v7.4s,v28.4s
208 sshl v16.4s,v16.4s,v28.4s
Dihevc_intra_pred_chroma_planar.s213 sshl v12.8h, v12.8h, v14.8h //shr
217 sshl v28.8h, v28.8h, v14.8h
237 sshl v26.8h, v26.8h, v14.8h //shr
243 sshl v24.8h, v24.8h, v14.8h
263 sshl v22.8h, v22.8h, v14.8h //shr
278 sshl v20.8h, v20.8h, v14.8h
289 sshl v12.8h, v12.8h, v14.8h //shr
291 sshl v28.8h, v28.8h, v14.8h
Dihevc_weighted_pred_bi.s237 sshl v4.4s,v4.4s,v28.4s //vshlq_s32(i4_tmp1_t1, tmp_shift_t)
249 sshl v6.4s,v6.4s,v28.4s
259 sshl v19.4s,v19.4s,v28.4s
271 sshl v18.4s,v18.4s,v28.4s
Dihevc_intra_pred_luma_dc.s195 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
448 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
/external/llvm-project/llvm/test/CodeGen/X86/
Dsshl_sat.ll5 declare i4 @llvm.sshl.sat.i4 (i4, i4)
6 declare i8 @llvm.sshl.sat.i8 (i8, i8)
7 declare i15 @llvm.sshl.sat.i15 (i15, i15)
8 declare i16 @llvm.sshl.sat.i16 (i16, i16)
9 declare i18 @llvm.sshl.sat.i18 (i18, i18)
10 declare i32 @llvm.sshl.sat.i32 (i32, i32)
11 declare i64 @llvm.sshl.sat.i64 (i64, i64)
51 %tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 %y)
102 %tmp = call i15 @llvm.sshl.sat.i15(i15 %x2, i15 %y2)
156 %tmp = call i15 @llvm.sshl.sat.i15(i15 %x, i15 %y3)
[all …]
Dsshl_sat_vec.ll5 declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
144 %tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dsaturating-intrinsics.ll10 declare i32 @llvm.sshl.sat.i32(i32, i32)
70 ; CHECK-NEXT: %z = call i32 @llvm.sshl.sat.i32(i32 %x, i32 %y)
74 %z = call i32 @llvm.sshl.sat.i32(i32 %x, i32 %y)
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsrem-seteq-vec-nonsplat.ll22 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
100 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
132 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
166 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
198 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
233 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
289 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
344 ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
379 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
413 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
[all …]
Darm64-vshr.ll6 ; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
22 ; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
Darm64-vshift.ll1303 declare <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8>, <16 x i8>)
1304 declare <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16>, <8 x i16>)
1305 declare <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32>, <4 x i32>)
1306 declare <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64>, <2 x i64>)
1312 …%tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1,…
1318 ;CHECK: sshl.16b {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
1320 …%tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 6, i8 1, i8 1,…
1326 ;CHECK: sshl.16b {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
1328 …%tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -2, i8 -2, i8 …
1337 …%tmp3 = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16…
[all …]
Dshift-by-signext.ll70 ; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
Dsve-fixed-length-int-shifts.ll31 ; CHECK-NEXT: sshl v0.8b, v0.8b, v1.8b
41 ; CHECK-NEXT: sshl v0.16b, v0.16b, v1.16b
124 ; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
134 ; CHECK-NEXT: sshl v0.8h, v0.8h, v1.8h
218 ; CHECK-NEXT: sshl v0.2s, v0.2s, v1.2s
228 ; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
312 ; CHECK-NEXT: sshl d0, d0, d1
322 ; CHECK-NEXT: sshl v0.2d, v0.2d, v1.2d
/external/llvm/test/CodeGen/AArch64/
Darm64-vshr.ll6 ; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
22 ; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dirtranslator-sat.ll413 %res = call i16 @llvm.sshl.sat.i16(i16 %lhs, i16 %rhs)
416 declare i16 @llvm.sshl.sat.i16(i16, i16)
429 %res = call i32 @llvm.sshl.sat.i32(i32 %lhs, i32 %rhs)
432 declare i32 @llvm.sshl.sat.i32(i32, i32)
451 %res = call i64 @llvm.sshl.sat.i64(i64 %lhs, i64 %rhs)
454 declare i64 @llvm.sshl.sat.i64(i64, i64)
473 %res = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
476 declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32>, <2 x i32>)

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