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Searched refs:stencil_irb (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c205 struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); in brw_workaround_depthstencil_alignment() local
230 invalidate_depth = invalidate_stencil && stencil_irb; in brw_workaround_depthstencil_alignment()
237 if (stencil_irb && in brw_workaround_depthstencil_alignment()
238 stencil_irb != depth_irb && in brw_workaround_depthstencil_alignment()
239 stencil_irb->mt == depth_mt) { in brw_workaround_depthstencil_alignment()
240 intel_miptree_reference(&stencil_irb->mt, depth_irb->mt); in brw_workaround_depthstencil_alignment()
241 intel_renderbuffer_set_draw_offset(stencil_irb); in brw_workaround_depthstencil_alignment()
245 if (stencil_irb) { in brw_workaround_depthstencil_alignment()
246 assert(stencil_irb->mt == depth_irb->mt); in brw_workaround_depthstencil_alignment()
247 assert(stencil_irb->mt_level == depth_irb->mt_level); in brw_workaround_depthstencil_alignment()
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Dbrw_draw.c720 struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); in brw_postdraw_set_buffers_need_resolve() local
748 if (stencil_irb && brw->stencil_write_enabled) { in brw_postdraw_set_buffers_need_resolve()
750 stencil_irb->mt->stencil_mt != NULL ? in brw_postdraw_set_buffers_need_resolve()
751 stencil_irb->mt->stencil_mt : stencil_irb->mt; in brw_postdraw_set_buffers_need_resolve()
753 intel_miptree_finish_write(brw, stencil_mt, stencil_irb->mt_level, in brw_postdraw_set_buffers_need_resolve()
754 stencil_irb->mt_layer, in brw_postdraw_set_buffers_need_resolve()
755 stencil_irb->layer_count, ISL_AUX_USAGE_NONE); in brw_postdraw_set_buffers_need_resolve()
808 struct intel_renderbuffer *stencil_irb = in brw_postdraw_reconcile_align_wa_slices() local
814 if (stencil_irb && stencil_irb->align_wa_mt) in brw_postdraw_reconcile_align_wa_slices()
815 intel_renderbuffer_move_temp_back(brw, stencil_irb); in brw_postdraw_reconcile_align_wa_slices()