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Searched refs:stencil_only_pipeline (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_meta_blit2d.c238 cmd_buffer->device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]; in bind_stencil_pipeline()
351 if (device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type] == VK_NULL_HANDLE) { in radv_meta_blit2d_normal_dst()
725 state->blit2d[log2_samples].stencil_only_pipeline[src], in radv_device_finish_meta_blit2d_state()
1128 if (device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]) { in blit2d_init_stencil_only_pipeline()
1315 &device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]); in blit2d_init_stencil_only_pipeline()
Dradv_meta_clear.c362 state->clear[i].stencil_only_pipeline[j], in radv_device_finish_meta_clear_state()
779 &meta_state->clear[samples_log2].stencil_only_pipeline[index]; in pick_depthstencil_pipeline()
1399 &state->clear[i].stencil_only_pipeline[j], in radv_device_init_meta_clear_state()
Dradv_private.h493 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; member
542 VkPipeline stencil_only_pipeline[5]; member