| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s | 18 stlexh r4, r2, [r5]
22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
|
| D | load-store-acquire-release-v8.s | 18 stlexh r4, r2, [r5]
22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
|
| D | thumbv8m.s | 136 stlexh r1, r2, [r3] label
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s | 18 stlexh r4, r2, [r5]
22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
|
| D | load-store-acquire-release-v8.s | 18 stlexh r4, r2, [r5]
22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
|
| D | thumbv8m.s | 136 stlexh r1, r2, [r3] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8.s.cs | 7 0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5]
|
| D | load-store-acquire-release-v8-thumb.s.cs | 7 0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5]
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8.txt | 16 # CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
|
| D | load-store-acquire-release-v8-thumb.txt | 17 # CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 17 # CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
|
| D | load-store-acquire-release-v8.txt | 16 # CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 76 ; CHECK: stlexh r0, r1, [r2]
|
| D | atomic-ops-v8.ll | 143 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
431 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
525 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]]
622 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]
1084 ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 76 ; CHECK: stlexh r0, r1, [r2]
|
| D | atomic-ops-v8.ll | 143 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
431 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
525 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]]
622 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]
1085 ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3296 void stlexh(Condition cond,
3300 void stlexh(Register rd, Register rt, const MemOperand& operand) { in stlexh() function
3301 stlexh(al, rd, rt, operand); in stlexh()
|
| D | disasm-aarch32.h | 1217 void stlexh(Condition cond,
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 949 { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */
6163 { /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 949 { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */
6163 { /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3404 "stlexh", "\t$Rd, $Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4738 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3627 "stlexh", "\t$Rd, $Rt, $addr", "",
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3696 "stlexh", "\t$Rd, $Rt, $addr", "",
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9909 "d\006stlexh\004stlh\003stm\005stmda\005stmdb\005stmib\003str\004strb\005"
11265 …{ 1503 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_Is…
11266 …{ 1503 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsAR…
|