| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 16 stllrb w0,[x1]
38 stllrb w0,[w1]
|
| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 16 stllrb w0,[x1]
38 stllrb w0,[w1]
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 15 # CHECK: stllrb w0, [x1]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 15 # CHECK: stllrb w0, [x1]
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1631 COMPARE(stllrb(w7, MemOperand(x8)), "stllrb w7, [x8]"); in TEST()
1632 COMPARE(stllrb(w9, MemOperand(sp)), "stllrb w9, [sp]"); in TEST()
1633 COMPARE(stllrb(x10, MemOperand(x11)), "stllrb w10, [x11]"); in TEST()
1634 COMPARE(stllrb(x12, MemOperand(sp)), "stllrb w12, [sp]"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 3525 TEST_LOREGIONS(stllrb_0, stllrb(w0, MemOperand(x1, 0)))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1369 void stllrb(const Register& rt, const MemOperand& dst);
|
| D | assembler-aarch64.cc | 1598 void Assembler::stllrb(const Register& rt, const MemOperand& dst) { in stllrb() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 2399 stllrb(rt, dst); in Stllrb()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2523 void stllrb(const Register& rt, const MemOperand& dst)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2485 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3500 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3294 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12586 "stllrb\006stllrh\004stlr\005stlrb\005stlrh\005stlur\006stlurb\006stlurh"
18746 …{ 5484 /* stllrb */, AArch64::STLLRB, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
26119 …{ 5484 /* stllrb */, AArch64::STLLRB, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
38695 { 5484 /* stllrb */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
38696 { 5484 /* stllrb */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
|