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Searched refs:strexd (Results 1 – 25 of 69) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Dinlineasm-64bit.ll7 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
8 …%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A te…
16 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
17 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
18 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
19 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
20 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
21 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
23 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
24 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
[all …]
Datomic-64bit.ll14 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
26 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
43 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
55 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
72 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
84 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
101 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
113 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
130 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
142 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
[all …]
DPR15053.ll4 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
11 %2 = tail call i32 @llvm.arm.strexd(i32 %1, i32 undef, i8* undef) nounwind
Dldstrex.ll23 ; CHECK: strexd
29 %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
30 ret i32 %strexd
34 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
Dldstrex-m.ll14 ; CHECK-NOT: strexd
23 ; CHECK-NOT: strexd
Dcmpxchg-O0.ll74 ; CHECK: strexd [[STATUS]], r4, r5, [r0]
92 ; CHECK: strexd [[STATUS]], {{r[0-9]+}}, {{r[0-9]+}}, [r0]
108 ; CHECK: strexd
/external/llvm-project/llvm/test/CodeGen/ARM/
Dinlineasm-64bit.ll7 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
8 …%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A te…
16 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
17 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
18 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
19 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
20 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
21 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
23 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
24 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
[all …]
Datomic-64bit.ll14 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
26 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
43 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
55 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
72 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
84 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
101 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
113 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
130 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
142 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
[all …]
DPR15053.ll4 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
11 %2 = tail call i32 @llvm.arm.strexd(i32 %1, i32 undef, i8* undef) nounwind
Dldstrex-m.ll14 ; CHECK-NOT: strexd
23 ; CHECK-NOT: strexd
Dldstrex.ll23 ; CHECK: strexd
29 %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
30 ret i32 %strexd
34 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
Dcmpxchg-O0.ll89 ; CHECK: strexd [[STATUS:[lr0-9]+]], r8, r9, [r1]
108 ; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
124 ; CHECK: strexd
Datomic-ops-v8.ll96 ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
288 ; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
480 ; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
569 ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]]
794 ; CHECK-ARM: strexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
795 ; CHECK-THUMB: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
1157 ; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Darm-STREXD-reencoding.txt9 # CHECK: strexd r1, r2, r3, [r0] @ encoding: [0x92,0x1f,0xa0,0xe1]
10 # CHECK: strexd r4, r0, r1, [r3] @ encoding: [0x90,0x4f,0xa3,0xe1]
11 # CHECK: strexd sp, r2, r3, [r4] @ encoding: [0x92,0xdf,0xa4,0xe1]
12 # CHECK: strexd r10, r0, r1, [r6] @ encoding: [0x90,0xaf,0xa6,0xe1]
13 # CHECK: strexd r5, r12, sp, [r8] @ encoding: [0x9c,0x5f,0xa8,0xe1]
Dinvalid-thumbv7-xfail.txt5 # Undefined encodings for ldrexd/strexd
35 # FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]"
/external/llvm/test/MC/Disassembler/ARM/
Darm-STREXD-reencoding.txt9 # CHECK: strexd r1, r2, r3, [r0] @ encoding: [0x92,0x1f,0xa0,0xe1]
10 # CHECK: strexd r4, r0, r1, [r3] @ encoding: [0x90,0x4f,0xa3,0xe1]
11 # CHECK: strexd sp, r2, r3, [r4] @ encoding: [0x92,0xdf,0xa4,0xe1]
12 # CHECK: strexd r10, r0, r1, [r6] @ encoding: [0x90,0xaf,0xa6,0xe1]
13 # CHECK: strexd r5, r12, sp, [r8] @ encoding: [0x9c,0x5f,0xa8,0xe1]
Dinvalid-thumbv7-xfail.txt5 # Undefined encodings for ldrexd/strexd
35 # FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]"
/external/llvm-project/llvm/test/MC/ARM/
Dthumb2-ldrexd-strexd.s8 strexd r3, r4, r5, [r6]
11 @ CHECK: strexd r3, r4, r5, [r6] @ encoding: [0xc6,0xe8,0x73,0x45]
Dthumbv8m.s87 strexd r0, r1, r2, [r3] label
/external/llvm/test/MC/ARM/
Dthumb2-ldrexd-strexd.s8 strexd r3, r4, r5, [r6]
11 @ CHECK: strexd r3, r4, r5, [r6] @ encoding: [0xc6,0xe8,0x73,0x45]
Dthumbv8m.s87 strexd r0, r1, r2, [r3] label
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll26 %strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
27 ret i32 %strexd
165 %strexd = tail call i32 @llvm.aarch64.stlxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
166 ret i32 %strexd
/external/llvm-project/compiler-rt/lib/builtins/arm/
Dsync-ops.h42 strexd r6, r4, r5, [r12]; \
/external/compiler-rt/lib/builtins/arm/
Dsync-ops.h45 strexd r6, r4, r5, [r12] ; \
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll27 %strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
28 ret i32 %strexd
204 %strexd = tail call i32 @llvm.aarch64.stlxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
205 ret i32 %strexd

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