| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsub.ll | 5 ;CHECK: subhn.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
14 ;CHECK: subhn.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
23 ;CHECK: subhn.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
32 ;CHECK: subhn.8b
34 %vsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
35 …%vsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nou…
42 ;CHECK: subhn.4h
[all …]
|
| D | arm64-vadd.ll | 876 ;CHECK: subhn.8b
887 ;CHECK: subhn.4h
898 ;CHECK: subhn.2s
|
| D | arm64-neon-3vdiff.ll | 811 ; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
821 ; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
831 ; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
841 ; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
851 ; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
861 ; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsub.ll | 5 ;CHECK: subhn.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
14 ;CHECK: subhn.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
23 ;CHECK: subhn.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
32 ;CHECK: subhn.8b
34 %vsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
35 …%vsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nou…
42 ;CHECK: subhn.4h
[all …]
|
| D | arm64-vadd.ll | 940 ;CHECK: subhn.8b
951 ;CHECK: subhn.4h
962 ;CHECK: subhn.2s
|
| D | arm64-neon-3vdiff.ll | 811 ; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
821 ; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
831 ; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
841 ; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
851 ; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
861 ; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2115 __ subhn(v5.V2S(), v14.V2D(), v13.V2D()); in GenerateTestSequenceNEON() local
2116 __ subhn(v10.V4H(), v5.V4S(), v8.V4S()); in GenerateTestSequenceNEON() local
2117 __ subhn(v6.V8B(), v10.V8H(), v22.V8H()); in GenerateTestSequenceNEON() local
|
| D | test-cpu-features-aarch64.cc | 2377 TEST_NEON(subhn_0, subhn(v0.V8B(), v1.V8H(), v2.V8H()))
2378 TEST_NEON(subhn_1, subhn(v0.V4H(), v1.V4S(), v2.V4S()))
2379 TEST_NEON(subhn_2, subhn(v0.V2S(), v1.V2D(), v2.V2D()))
|
| D | test-simulator-aarch64.cc | 4687 DEFINE_TEST_NEON_3DIFF_NARROW(subhn, Basic)
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 1775 0x~~~~~~~~~~~~~~~~ 0ead61c5 subhn v5.2s, v14.2d, v13.2d
1776 0x~~~~~~~~~~~~~~~~ 0e6860aa subhn v10.4h, v5.4s, v8.4s
1777 0x~~~~~~~~~~~~~~~~ 0e366146 subhn v6.8b, v10.8h, v22.8h
|
| D | log-disasm | 1775 0x~~~~~~~~~~~~~~~~ 0ead61c5 subhn v5.2s, v14.2d, v13.2d
1776 0x~~~~~~~~~~~~~~~~ 0e6860aa subhn v10.4h, v5.4s, v8.4s
1777 0x~~~~~~~~~~~~~~~~ 0e366146 subhn v6.8b, v10.8h, v22.8h
|
| D | log-cpufeatures-custom | 1774 0x~~~~~~~~~~~~~~~~ 0ead61c5 subhn v5.2s, v14.2d, v13.2d ### {NEON} ###
1775 0x~~~~~~~~~~~~~~~~ 0e6860aa subhn v10.4h, v5.4s, v8.4s ### {NEON} ###
1776 0x~~~~~~~~~~~~~~~~ 0e366146 subhn v6.8b, v10.8h, v22.8h ### {NEON} ###
|
| D | log-cpufeatures-colour | 1774 0x~~~~~~~~~~~~~~~~ 0ead61c5 subhn v5.2s, v14.2d, v13.2d [1;35mNEON[0;m
1775 0x~~~~~~~~~~~~~~~~ 0e6860aa subhn v10.4h, v5.4s, v8.4s [1;35mNEON[0;m
1776 0x~~~~~~~~~~~~~~~~ 0e366146 subhn v6.8b, v10.8h, v22.8h [1;35mNEON[0;m
|
| D | log-cpufeatures | 1774 0x~~~~~~~~~~~~~~~~ 0ead61c5 subhn v5.2s, v14.2d, v13.2d // Needs: NEON
1775 0x~~~~~~~~~~~~~~~~ 0e6860aa subhn v10.4h, v5.4s, v8.4s // Needs: NEON
1776 0x~~~~~~~~~~~~~~~~ 0e366146 subhn v6.8b, v10.8h, v22.8h // Needs: NEON
|
| D | log-all | 8804 0x~~~~~~~~~~~~~~~~ 0ead61c5 subhn v5.2s, v14.2d, v13.2d
8806 0x~~~~~~~~~~~~~~~~ 0e6860aa subhn v10.4h, v5.4s, v8.4s
8808 0x~~~~~~~~~~~~~~~~ 0e366146 subhn v6.8b, v10.8h, v22.8h
|
| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 7553 { /* AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN: subhn.2s $rd, $rn, $rm */
7561 { /* AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN: subhn.4h $rd, $rn, $rm */
7573 { /* AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN: subhn.8b $rd, $rn, $rm */
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 3912 V(subhn) \
|
| D | assembler-aarch64.h | 3424 void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | logic-aarch64.cc | 4125 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 2482 V(subhn, NEON_SUBHN, vd.IsD()) \
|
| D | macro-assembler-aarch64.h | 2782 V(subhn, Subhn) \
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3534 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3624 // CodeGen patterns for addhn and subhn instructions, which can actually be
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 5539 void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4660 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
4769 // CodeGen patterns for addhn and subhn instructions, which can actually be
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4478 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
4587 // CodeGen patterns for addhn and subhn instructions, which can actually be
|