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Searched refs:subnr (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_reg.h225 unsigned subnr:5; /* :1 in align16 */ member
405 unsigned subnr, in brw_reg() argument
431 reg.subnr = subnr * type_sz(type); in brw_reg()
452 brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) in brw_vec16_reg() argument
456 subnr, in brw_vec16_reg()
469 brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) in brw_vec8_reg() argument
473 subnr, in brw_vec8_reg()
486 brw_vec4_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) in brw_vec4_reg() argument
490 subnr, in brw_vec4_reg()
503 brw_vec2_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) in brw_vec2_reg() argument
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Dbrw_ir_vec4.h86 const unsigned suboffset = reg->subnr + bytes; in add_byte_offset()
88 reg->subnr = suboffset % REG_SIZE; in add_byte_offset()
89 assert(reg->subnr % 16 == 0); in add_byte_offset()
236 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0); in reg_offset()
Dbrw_eu_emit.c118 assert(dest.subnr == 0); in brw_set_dest()
132 assert(dest.subnr % 16 == 0); in brw_set_dest()
137 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); in brw_set_dest()
147 brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr); in brw_set_dest()
152 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); in brw_set_dest()
165 brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr); in brw_set_dest()
239 assert(reg.subnr == 0); in brw_set_src0()
251 assert(reg.subnr % 16 == 0); in brw_set_src0()
257 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16); in brw_set_src0()
284 brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr); in brw_set_src0()
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Dbrw_vec4.cpp703 assert(inst->src[0].subnr == 0); in pack_uniform_registers()
1636 fprintf(file, "a0.%d", inst->dst.subnr); in dump_instruction()
1639 fprintf(file, "acc%d", inst->dst.subnr); in dump_instruction()
1642 fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); in dump_instruction()
1645 fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); in dump_instruction()
1690 fprintf(file, "g%d.%d", inst->src[i].nr, inst->src[i].subnr); in dump_instruction()
1730 fprintf(file, "a0.%d", inst->src[i].subnr); in dump_instruction()
1733 fprintf(file, "acc%d", inst->src[i].subnr); in dump_instruction()
1736 fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); in dump_instruction()
1739 fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); in dump_instruction()
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Dbrw_ir_fs.h91 const unsigned suboffset = reg.subnr + delta; in byte_offset()
93 reg.subnr = suboffset % REG_SIZE; in byte_offset()
185 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0); in reg_offset()
Dbrw_ir.h72 using brw_reg::subnr;
Dbrw_vec4_generator.cpp1414 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2); in generate_mov_indirect()
1423 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2; in generate_mov_indirect()
1441 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0)); in generate_mov_indirect()
1447 indirect.subnr *= 2; in generate_mov_indirect()
2049 dst.subnr = offset * 4; in generate_code()
2055 src[0].subnr = 16; in generate_code()
2056 dst.subnr = 16 + offset * 4; in generate_code()
Dbrw_fs_generator.cpp464 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr; in generate_mov_indirect()
470 reg.subnr = imm_byte_offset % REG_SIZE; in generate_mov_indirect()
653 uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr; in generate_shuffle()
2257 src[0].subnr = 0 * type_sz(src[0].type); in generate_code()
2262 src[0].subnr = 4 * type_sz(src[0].type); in generate_code()
Dbrw_fs_copy_propagation.cpp617 inst->src[arg].subnr = entry->src.subnr; in try_copy_propagate()
Dtest_eu_validate.cpp1553 unsigned subnr; in TEST_P() member
1557 #define INST(dst_type, src0_type, src1_type, dst_stride, read_acc, subnr, \ in TEST_P() argument
1565 subnr, \ in TEST_P()
1604 brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr); in TEST_P()
2063 unsigned subnr; in TEST_P() member
2087 brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, move[i].subnr); in TEST_P()
Dbrw_fs.cpp1083 const unsigned start = (r.nr - BRW_ARF_FLAG) * 4 + r.subnr; in flag_mask()
5380 sample_mask.subnr == brw_flag_subreg( in emit_predicate_on_sample_mask()
5381 subreg + inst->group / 16).subnr); in emit_predicate_on_sample_mask()
7276 fprintf(file, "a0.%d", inst->dst.subnr); in dump_instruction()
7279 fprintf(file, "acc%d", inst->dst.subnr); in dump_instruction()
7282 fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); in dump_instruction()
7285 fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); in dump_instruction()
7374 fprintf(file, "a0.%d", inst->src[i].subnr); in dump_instruction()
7377 fprintf(file, "acc%d", inst->src[i].subnr); in dump_instruction()
7380 fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); in dump_instruction()
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/external/igt-gpu-tools/assembler/
Dbrw_reg.h116 unsigned subnr:5; /* :1 in align16 */ member
182 unsigned subnr, in brw_reg() argument
201 reg.subnr = subnr * type_sz(type); in brw_reg()
225 brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr) in brw_vec16_reg() argument
229 subnr, in brw_vec16_reg()
240 brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr) in brw_vec8_reg() argument
244 subnr, in brw_vec8_reg()
255 brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr) in brw_vec4_reg() argument
259 subnr, in brw_vec4_reg()
270 brw_vec2_reg(unsigned file, unsigned nr, unsigned subnr) in brw_vec2_reg() argument
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Dgen8_instruction.c55 gen8_set_dst_da1_subreg_nr(inst, reg.subnr); in gen8_set_dst()
63 assert(reg.subnr == 0 || reg.subnr == 16); in gen8_set_dst()
64 gen8_set_dst_da16_subreg_nr(inst, reg.subnr >> 4); in gen8_set_dst()
76 gen8_set_dst_ida1_sub_nr(inst, reg.subnr); in gen8_set_dst()
190 gen8_set_src0_da1_subreg_nr(inst, reg.subnr); in gen8_set_src0()
204 assert(reg.subnr == 0 || reg.subnr == 16); in gen8_set_src0()
205 gen8_set_src0_da16_subreg_nr(inst, reg.subnr >> 4); in gen8_set_src0()
240 gen8_set_src0_ida1_sub_nr(inst, reg.subnr); in gen8_set_src0()
279 gen8_set_src1_da1_subreg_nr(inst, reg.subnr); in gen8_set_src1()
292 assert(reg.subnr == 0 || reg.subnr == 16); in gen8_set_src1()
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Dgram.y425 reg->subnr = get_subreg_address(reg->file, reg->type, reg->subnr, in resolve_subnr()
428 reg->subnr = get_indirect_subreg_address(reg->subnr); in resolve_subnr()
1186 src0.reg.subnr = 0;
1311 src0.reg.subnr = 0;
1337 $7.reg.subnr != 0) {
1361 src0.reg.subnr = 0;
2097 $$.reg.nr += ($$.reg.subnr + $5) / (32 / size);
2098 $$.reg.subnr = ($$.reg.subnr + $5) % (32 / size);
2100 $$.reg.nr += ($$.reg.subnr + $5) / 32;
2101 $$.reg.subnr = ($$.reg.subnr + $5) % 32;
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Dbrw_eu_debug.c60 hwreg.subnr == 0 && in brw_print_reg()
74 printf("scl%d.%d", hwreg.nr, hwreg.subnr / 4); in brw_print_reg()
83 hwreg.subnr / type_sz(hwreg.type), in brw_print_reg()
Dbrw_eu_emit.c122 insn->bits1.da1.dest_subreg_nr = dest.subnr; in brw_set_dest()
128 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16; in brw_set_dest()
135 insn->bits1.ia1.dest_subreg_nr = dest.subnr; in brw_set_dest()
295 insn->bits2.da1.src0_subreg_nr = reg.subnr; in brw_set_src0()
299 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16; in brw_set_src0()
304 insn->bits2.ia1.src0_subreg_nr = reg.subnr; in brw_set_src0()
386 insn->bits3.da1.src1_subreg_nr = reg.subnr; in brw_set_src1()
390 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16; in brw_set_src1()
395 insn->bits3.ia1.src1_subreg_nr = reg.subnr; in brw_set_src1()
810 return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0); in get_3src_subreg_nr()
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/external/mesa3d/src/intel/tools/
Di965_gram.y88 reg->subnr, in set_direct_src_operand()
1005 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
1514 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1525 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1681 $1.subnr,
1718 $3.subnr,
1747 $3.subnr,
1765 $$.subnr = $1.subnr;
1788 $$.subnr = $2;
1797 $$.subnr = $3.subnr;
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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_ff_gs_emit.c439 vertex_slot.subnr = (slot % 2) * 16; in gen6_sol_program()
/external/mesa3d/docs/relnotes/
D20.2.0.rst2563 - intel/eu: Set the right subnr for ALIGN16 destinations
3438 - intel/tools: Manually set ARF register file/nr/subnr