Searched refs:surf_info (Results 1 – 3 of 3) sorted by relevance
39 static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info, in radv_amdgpu_surface_sanity() argument49 if (surf_info->height > 1) in radv_amdgpu_surface_sanity()54 if (surf_info->depth > 1 || surf_info->array_size > 1) in radv_amdgpu_surface_sanity()58 if (surf_info->array_size > 1) in radv_amdgpu_surface_sanity()62 if (surf_info->height > 1) in radv_amdgpu_surface_sanity()66 if (surf_info->depth > 1) in radv_amdgpu_surface_sanity()76 const struct ac_surf_info *surf_info, in radv_amdgpu_winsys_surface_init() argument83 r = radv_amdgpu_surface_sanity(surf_info, surf); in radv_amdgpu_winsys_surface_init()92 memcpy(&config.info, surf_info, sizeof(config.info)); in radv_amdgpu_winsys_surface_init()
1408 const struct isl_surf_init_info *surf_info, in isl_calc_row_pitch_alignment() argument1423 isl_format_supports_ccs_e(dev->info, surf_info->format) && in isl_calc_row_pitch_alignment()1425 !(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) && in isl_calc_row_pitch_alignment()1426 surf_info->row_pitch_B == 0) { in isl_calc_row_pitch_alignment()1447 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); in isl_calc_row_pitch_alignment()1451 if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { in isl_calc_row_pitch_alignment()1452 if (isl_format_is_yuv(surf_info->format)) { in isl_calc_row_pitch_alignment()1466 if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) in isl_calc_row_pitch_alignment()1486 const struct isl_surf_init_info *surf_info, in isl_calc_tiled_min_row_pitch() argument1491 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); in isl_calc_tiled_min_row_pitch()[all …]
303 const struct ac_surf_info *surf_info,