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Searched refs:surf_offset (Results 1 – 25 of 25) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_wm_surface_state.c141 uint32_t *surf_offset, int surf_index, in brw_emit_surface_state() argument
175 surf_offset); in brw_emit_surface_state()
179 *surf_offset + brw->isl_dev.ss.addr_offset, in brw_emit_surface_state()
202 *surf_offset + in brw_emit_surface_state()
209 *surf_offset + in brw_emit_surface_state()
223 *surf_offset + in brw_emit_surface_state()
466 uint32_t *surf_offset, in brw_update_texture_surface() argument
476 brw_update_buffer_texture_surface(ctx, unit, surf_offset); in brw_update_texture_surface()
586 const int surf_index = surf_offset - &brw->wm.base.surf_offset[0]; in brw_update_texture_surface()
618 surf_offset, surf_index, in brw_update_texture_surface()
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Dgen6_sol.c62 &brw->gs.base.surf_offset[surf_index], in gen6_update_sol_surfaces()
68 &brw->ff_gs.surf_offset[surf_index], in gen6_update_sol_surfaces()
74 brw->ff_gs.surf_offset[surf_index] = 0; in gen6_update_sol_surfaces()
76 brw->gs.base.surf_offset[surf_index] = 0; in gen6_update_sol_surfaces()
140 memcpy(bind, brw->ff_gs.surf_offset, in brw_gs_upload_binding_table()
168 memcpy(bind, brw->gs.base.surf_offset, in brw_gs_upload_binding_table()
Dgen6_constant_state.c242 if (stage_state->surf_offset[surf_index]) { in brw_upload_pull_constants()
243 stage_state->surf_offset[surf_index] = 0; in brw_upload_pull_constants()
275 brw_emit_buffer_surface_state(brw, &stage_state->surf_offset[surf_index], in brw_upload_pull_constants()
Dbrw_binding_tables.c71 brw, &stage_state->surf_offset[ in brw_upload_binding_table()
81 memcpy(bind, stage_state->surf_offset, in brw_upload_binding_table()
Dbrw_context.h652 uint32_t surf_offset[BRW_MAX_SURFACES]; member
1124 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS]; member
1412 uint32_t *surf_offset);
DgenX_state_upload.c4278 brw, &stage_state->surf_offset[
4381 memcpy(bind, stage_state->surf_offset,
/external/mesa3d/src/gallium/drivers/radeonsi/
Dcik_sdma.c64 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
65 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
80 assert(sdst->surface.u.gfx9.surf_offset + dst_slice_pitch * bpp * (dstz + src_box->depth) <= in si_sdma_v4_copy_texture()
82 assert(ssrc->surface.u.gfx9.surf_offset + src_slice_pitch * bpp * (srcz + src_box->depth) <= in si_sdma_v4_copy_texture()
Dsi_texture.c194 return tex->surface.u.gfx9.surf_offset + box->z * tex->surface.u.gfx9.surf_slice_size + in si_texture_get_offset()
621 *value = tex->surface.u.gfx9.surf_offset + layer * tex->surface.u.gfx9.surf_slice_size; in si_resource_get_param()
Dsi_state.c2411 assert(tex->surface.u.gfx9.surf_offset == 0); in si_init_depth_surface()
2963 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; in si_emit_framebuffer_state()
3010 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; in si_emit_framebuffer_state()
Dsi_descriptors.c318 va += tex->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_dec_jpeg.c47 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
49 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
Dradeon_vcn_enc_1_2.c995 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params()
996 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params()
1040 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
1041 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
Dradeon_vcn_dec.c1040 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in rvcn_dec_message_decode()
1041 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in rvcn_dec_message_decode()
1044 luma->surface.u.gfx9.surf_offset + luma->surface.u.gfx9.surf_slice_size; in rvcn_dec_message_decode()
1046 chroma->surface.u.gfx9.surf_offset + chroma->surface.u.gfx9.surf_slice_size; in rvcn_dec_message_decode()
Dradeon_vce_52.c276 enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo in encode()
278 enc->chroma->u.gfx9.surf_offset); // inputPictureChromaAddressHi/Lo in encode()
Dradeon_uvd_enc_1_1.c904 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_uvd_enc_encode_params_hevc()
905 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_uvd_enc_encode_params_hevc()
Dradeon_uvd.c1387 return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size; in texture_offset()
/external/mesa3d/src/amd/common/
Dac_surface.h161 uint64_t surf_offset; /* 0 unless imported with an offset */ member
Dac_surface.c1946 surf->u.gfx9.surf_offset = 0; in gfx9_compute_surface()
2320 offset = surf->u.gfx9.surf_offset; in ac_surface_set_umd_metadata()
2468 surf->u.gfx9.surf_offset = offset; in ac_surface_override_offset_stride()
/external/mesa3d/docs/relnotes/
D20.0.7.rst71 - i965: Fix out-of-bounds access to brw_stage_state::surf_offset
D19.3.0.rst2738 - radeonsi: use gfx9.surf_offset to compute texture offset
D20.0.0.rst2693 - radeonsi: use gfx9.surf_offset to compute texture offset
D20.1.0.rst1320 - i965: Fix out-of-bounds access to brw_stage_state::surf_offset
D20.2.0.rst1307 - i965: Fix out-of-bounds access to brw_stage_state::surf_offset
/external/mesa3d/src/amd/vulkan/
Dradv_image.c644 va += plane->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
Dradv_device.c6761 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8; in radv_initialise_color_surface()
7036 assert(surf->u.gfx9.surf_offset == 0); in radv_initialise_ds_surface()