| /external/mesa3d/src/intel/isl/ |
| D | isl_storage_image.c | 220 .swizzling = { 0xff, 0xff },
278 param->swizzling[0] = 3; in isl_surf_fill_image_param()
279 param->swizzling[1] = 4; in isl_surf_fill_image_param()
296 param->swizzling[0] = 3; in isl_surf_fill_image_param()
297 param->swizzling[1] = 0xff; in isl_surf_fill_image_param()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 894 // and swizzling changes depending on whether idxen is set in the instruction.
896 // they behave differently in bounds checking and swizzling.
900 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
901 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
915 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
916 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
930 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
931 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
946 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
947 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
[all …]
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| /external/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 932 // and swizzling changes depending on whether idxen is set in the instruction.
934 // they behave differently in bounds checking and swizzling.
938 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
939 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
953 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
954 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
968 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
969 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
984 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
985 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
[all …]
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| /external/angle/src/libANGLE/renderer/metal/ |
| D | mtl_format_utils.mm | 147 // When texture swizzling is available, DXT1 RGB format will be swizzled with RGB1.
148 // WebGL allows unswizzled mapping when swizzling is not available. No need to convert.
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| /external/mesa3d/docs/relnotes/ |
| D | 8.0.2.rst | 76 - i965: fixup W-tile offset computation to take swizzling into account
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| D | 9.1.6.rst | 97 - i965/vs: Fix flaky texture swizzling
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| D | 20.0.3.rst | 93 - intel/blorp: Add support for swizzling fast-clear colors
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| D | 9.1.2.rst | 164 - i965: Don't use texture swizzling to force alpha to 1.0 if
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| D | 9.0.3.rst | 173 - i965: Do texture swizzling in hardware on Haswell.
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| D | 9.1.4.rst | 280 - r300g/compiler: Prevent regalloc from swizzling texture operands v2
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| D | 7.10.rst | 274 - llvmpipe: fix swizzling of texture border color
275 - softpipe: fix swizzling of texture border color
1074 - i965: Remove swizzling of assignment to vector-splitting
1149 - i965: Set up swizzling of shadow compare results for
1181 - i965: Enable attribute swizzling (repositioning) in the gen6 SF.
1279 - i965: Work around strangeness in swizzling/masking of gen6 math.
1373 - intel: Set the swizzling for depth textures using the GL_RED depth
2267 - r300g: fix swizzling of texture border color
2316 - r300/compiler: add a function for swizzling a mask
2325 - r300g: fix texture swizzling with compressed textures on r400-r500
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| D | 7.9.1.rst | 337 - r300g: fix texture swizzling with compressed textures on r400-r500
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_nir_uniforms.cpp | 110 offsetof(brw_image_param, swizzling), 2); in brw_setup_image_uniform_values()
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| D | brw_wm_surface_state.c | 1500 param->swizzling[0] = 0xff; in update_default_image_param()
1501 param->swizzling[1] = 0xff; in update_default_image_param()
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| D | genX_state_upload.c | 1036 bool swizzling = two_side_color && in genX() local
1043 if (*max_source_attr < source_attr + swizzling) in genX()
1044 *max_source_attr = source_attr + swizzling; in genX()
1047 if (swizzling) in genX()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_compiler.h | 534 uint32_t swizzling[2]; member
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| /external/mesa3d/docs/drivers/ |
| D | llvmpipe.rst | 254 Swizzling <http://devmaster.net/posts/12785/texture-swizzling>`__
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | spill-offset-calculation.ll | 6 ; swizzling.
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA55.td | 89 // An extra cycle is needed to get the swizzling right.
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| /external/mesa3d/docs/gallium/ |
| D | screen.rst | 40 * ``PIPE_CAP_TEXTURE_SWIZZLE``: Whether swizzling through sampler views is
170 and swizzling in gallium frontends. Generally, all hardware drivers with
586 …hether pipe_viewport_state::swizzle can be used to specify pre-clipping swizzling of coordinates (…
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| D | tgsi.rst | 2330 Note that the swizzle on SVIEW (src1) determines texel swizzling
2484 resinfo allowing swizzling dst values is ignored (due to the interaction
3609 subject to conversion, swizzling and scaling as required to yield
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPU.td | 353 // DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPU.td | 383 // DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_descriptor_set.c | 1254 WRITE_PARAM_FIELD(swizzling, SWIZZLING); in anv_descriptor_set_write_image_param()
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| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_program.c | 518 offsetof(struct brw_image_param, swizzling), 2); in iris_setup_uniforms()
|