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Searched refs:swm16 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/Mips/
Dmicromips-loadstore-instructions.s36 # CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
41 # CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
82 # CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
87 # CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
125 swm16 $16, $17, $ra, 8($sp)
Dmicromips-invalid.s28 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
29 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers…
30 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-loadstore-instructions.s46 # CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
56 # CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
105 # CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
115 # CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
151 swm16 $16, $17, $ra, 8($sp)
Dmicromips-invalid.s28 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
29 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers…
30 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s108 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
109 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers ex…
110 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
111 swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
112 swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
113 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
114 …swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
115 …swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s120 swm $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
121 swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s133 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
134 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers ex…
135 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
136 swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
137 swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
138 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
139 …swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
140 …swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s158 swm $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
159 swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
/external/llvm-project/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s111 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
112 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers ex…
113 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
114 swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
115 swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
116 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
117 …swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
118 …swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s152 swm $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
153 swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
/external/llvm-project/llvm/test/MC/Mips/micromips/
Dvalid.s84 swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52] label
/external/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid-el.txt48 0x52 0x45 # CHECK: swm16 $16, $17, $ra, 8($sp)
Dvalid.txt48 0x45 0x52 # CHECK: swm16 $16, $17, $ra, 8($sp)
/external/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid-el.txt49 0x52 0x45 # CHECK: swm16 $16, $17, $ra, 8($sp)
Dvalid.txt49 0x45 0x52 # CHECK: swm16 $16, $17, $ra, 8($sp)
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt166 0x45 0x2a # CHECK: swm16 $16, $17, $ra, 8($sp)
/external/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt262 0x45 0x2a # CHECK: swm16 $16, $17, $ra, 8($sp)
/external/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt258 0x45 0x2a # CHECK: swm16 $16, $17, $ra, 8($sp)
/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td1184 !strconcat("swm16", "\t$rt, $addr"), [],
1186 MMR6Arch<"swm16">, MicroMipsR6Inst16 {
DMicroMipsInstrInfo.td660 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>,
/external/llvm-project/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td1192 !strconcat("swm16", "\t$rt, $addr"), [],
1194 MMR6Arch<"swm16"> {
DMicroMipsInstrInfo.td704 def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td1192 !strconcat("swm16", "\t$rt, $addr"), [],
1194 MMR6Arch<"swm16"> {
DMicroMipsInstrInfo.td704 def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5103 "16\004swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm"
7933 …{ 9255 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_No…
7934 …{ 9255 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_…
11463 { 9255 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 },
11464 { 9255 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
11465 { 9255 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
11466 { 9255 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },