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/external/capstone/suite/MC/Mips/
Dmips-coprocessor-encodings.s.cs2 0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2
3 0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0
4 0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2
5 0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0
6 0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2
7 0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0
8 0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2
9 0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0
10 0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2
11 0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dn32.S78 ADDU t4, v0, 2 * FFI_SIZEOF_ARG -1 # make sure it is aligned
79 and v0, t4, -2 * FFI_SIZEOF_ARG # to a proper boundry.
110 and t4, t6, ((1<<FFI_FLAG_BITS)-1)
112 beqz t4, arg1_next
113 bne t4, FFI_TYPE_FLOAT, arg1_doublep
120 SRL t4, t6, 1*FFI_FLAG_BITS
121 and t4, ((1<<FFI_FLAG_BITS)-1)
123 beqz t4, arg2_next
124 bne t4, FFI_TYPE_FLOAT, arg2_doublep
131 SRL t4, t6, 2*FFI_FLAG_BITS
[all …]
/external/angle/third_party/vulkan-deps/glslang/src/Test/
Dspv.bufferhandle13.frag5 layout(set = 1, binding = 2, buffer_reference, std430) buffer t4 {
10 t4 m;
13 t4 f1(const t4 y) { return y; }
14 t4 f2(t4 y) { return y; }
15 t4 f3(const restrict t4 y) { return y; }
16 t4 f4(restrict t4 y) { return y; }
18 t4 g1;
19 restrict t4 g2;
23 t4 a = s5.m;
24 restrict t4 b = s5.m;
/external/deqp-deps/glslang/Test/
Dspv.bufferhandle13.frag5 layout(set = 1, binding = 2, buffer_reference, std430) buffer t4 {
10 t4 m;
13 t4 f1(const t4 y) { return y; }
14 t4 f2(t4 y) { return y; }
15 t4 f3(const restrict t4 y) { return y; }
16 t4 f4(restrict t4 y) { return y; }
18 t4 g1;
19 restrict t4 g2;
23 t4 a = s5.m;
24 restrict t4 b = s5.m;
/external/libffi/src/mips/
Dn32.S85 ADDU t4, v0, 2 * FFI_SIZEOF_ARG -1 # make sure it is aligned
86 and v0, t4, -2 * FFI_SIZEOF_ARG # to a proper boundry.
127 and t4, t6, ((1<<FFI_FLAG_BITS)-1)
129 beqz t4, arg1_next
130 bne t4, FFI_TYPE_FLOAT, arg1_doublep
137 SRL t4, t6, 1*FFI_FLAG_BITS
138 and t4, ((1<<FFI_FLAG_BITS)-1)
140 beqz t4, arg2_next
141 bne t4, FFI_TYPE_FLOAT, arg2_doublep
148 SRL t4, t6, 2*FFI_FLAG_BITS
[all …]
/external/mesa3d/src/freedreno/.gitlab-ci/reference/
DdEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log10 t4 write HLSQ_INVALIDATE_CMD (bb08)
15 t4 write RB_CCU_CNTL (8e07)
18 t4 write RB_UNKNOWN_8E04 (8e04)
21 t4 write SP_UNKNOWN_AE04 (ae04)
24 t4 write SP_UNKNOWN_AE00 (ae00)
27 t4 write SP_UNKNOWN_AE0F (ae0f)
30 t4 write SP_UNKNOWN_B605 (b605)
33 t4 write SP_UNKNOWN_B600 (b600)
36 t4 write HLSQ_UNKNOWN_BE00 (be00)
39 t4 write HLSQ_UNKNOWN_BE01 (be01)
[all …]
/external/speex/libspeexdsp/
Dsmallft.c119 int t0,t1,t2,t3,t4,t5,t6; in dradf2() local
138 t4=(t1<<1)+(ido<<1); in dradf2()
143 t4-=2; in dradf2()
149 ch[t4]=ti2-cc[t5]; in dradf2()
151 ch[t4-1]=cc[t5-1]-tr2; in dradf2()
174 int i,k,t0,t1,t2,t3,t4,t5,t6; in dradf4() local
179 t4=t1<<1; in dradf4()
185 tr2=cc[t3]+cc[t4]; in dradf4()
189 ch[(t5+=(ido<<1))-1]=cc[t3]-cc[t4]; in dradf4()
195 t4+=ido; in dradf4()
[all …]
/external/deqp-deps/glslang/Test/baseResults/
Dspv.bufferhandle3.frag.out17 Name 9 "t4"
18 MemberName 9(t4) 0 "j"
19 MemberName 9(t4) 1 "k"
28 Name 38 "t4"
29 MemberName 38(t4) 0 "j"
30 MemberName 38(t4) 1 "k"
33 MemberDecorate 9(t4) 0 Offset 0
34 MemberDecorate 9(t4) 1 Offset 8
35 Decorate 9(t4) Block
43 MemberDecorate 38(t4) 0 Offset 0
[all …]
Dspv.bufferhandle4.frag.out17 Name 8 "t4"
18 MemberName 8(t4) 0 "j"
19 MemberName 8(t4) 1 "k"
23 Name 11 "t4"
24 MemberName 11(t4) 0 "j"
25 MemberName 11(t4) 1 "k"
31 MemberDecorate 8(t4) 0 Offset 0
32 MemberDecorate 8(t4) 1 Offset 8
33 Decorate 8(t4) Block
37 MemberDecorate 11(t4) 0 Offset 0
[all …]
Dspv.bufferhandle5.frag.out16 Name 8 "t4"
17 MemberName 8(t4) 0 "j"
18 MemberName 8(t4) 1 "k"
22 MemberDecorate 8(t4) 0 Offset 0
23 MemberDecorate 8(t4) 1 Offset 8
24 Decorate 8(t4) Block
33 8(t4): TypeStruct 6(int) 7
36 10: TypePointer Uniform 8(t4)
/external/angle/third_party/vulkan-deps/glslang/src/Test/baseResults/
Dspv.bufferhandle3.frag.out17 Name 9 "t4"
18 MemberName 9(t4) 0 "j"
19 MemberName 9(t4) 1 "k"
28 Name 38 "t4"
29 MemberName 38(t4) 0 "j"
30 MemberName 38(t4) 1 "k"
33 MemberDecorate 9(t4) 0 Offset 0
34 MemberDecorate 9(t4) 1 Offset 8
35 Decorate 9(t4) Block
43 MemberDecorate 38(t4) 0 Offset 0
[all …]
Dspv.bufferhandle4.frag.out17 Name 8 "t4"
18 MemberName 8(t4) 0 "j"
19 MemberName 8(t4) 1 "k"
23 Name 11 "t4"
24 MemberName 11(t4) 0 "j"
25 MemberName 11(t4) 1 "k"
31 MemberDecorate 8(t4) 0 Offset 0
32 MemberDecorate 8(t4) 1 Offset 8
33 Decorate 8(t4) Block
37 MemberDecorate 11(t4) 0 Offset 0
[all …]
Dspv.bufferhandle5.frag.out16 Name 8 "t4"
17 MemberName 8(t4) 0 "j"
18 MemberName 8(t4) 1 "k"
22 MemberDecorate 8(t4) 0 Offset 0
23 MemberDecorate 8(t4) 1 Offset 8
24 Decorate 8(t4) Block
33 8(t4): TypeStruct 6(int) 7
36 10: TypePointer Uniform 8(t4)
/external/llvm-project/llvm/test/CodeGen/MSP430/
Dbit.ll39 %t4 = zext i1 %t3 to i8
40 ret i8 %t4
49 %t4 = zext i1 %t3 to i8
50 ret i8 %t4
59 %t4 = zext i1 %t3 to i8
60 ret i8 %t4
69 %t4 = zext i1 %t3 to i8
70 ret i8 %t4
79 %t4 = icmp ne i8 %t3, 0
80 %t5 = zext i1 %t4 to i8
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dicmp-logical.ll170 %t4 = and i1 %t3, %t2
171 ret i1 %t4
183 %t4 = or i1 %t3, %t2
184 ret i1 %t4
230 %t4 = icmp eq i32 %t3, 1
231 %t5 = and i1 %t2, %t4
245 %t4 = icmp eq i32 %t3, 1
246 %t5 = and i1 %t2, %t4
263 %t4 = icmp eq i32 %t3, 1
264 %t5 = and i1 %t2, %t4
[all …]
Dsigned-truncation-check.ll47 %t4 = and i1 %t1, %t3
48 ret i1 %t4
59 %t4 = icmp ult i32 %t3, 256
60 %t5 = and i1 %t2, %t4
72 %t4 = and i1 %t1, %t3
73 ret i1 %t4
85 %t4 = and i1 %t1, %t3
86 ret i1 %t4
102 %t4 = and i1 %t1, %z
103 %t5 = and i1 %t3, %t4
[all …]
Dshift-amount-reassociation-with-truncation-lshr.ll23 %t4 = add i16 %y, -1
24 %t5 = lshr i16 %t3, %t4
40 %t4 = add <2 x i16> %y, <i16 -1, i16 -1>
41 %t5 = lshr <2 x i16> %t3, %t4
55 %t4 = add <3 x i16> %y, <i16 -1, i16 -1, i16 -1>
56 %t5 = lshr <3 x i16> %t3, %t4
70 %t4 = add <3 x i16> %y, <i16 -1, i16 undef, i16 -1>
71 %t5 = lshr <3 x i16> %t3, %t4
85 %t4 = add <3 x i16> %y, <i16 -1, i16 undef, i16 -1>
86 %t5 = lshr <3 x i16> %t3, %t4
[all …]
Dshift-amount-reassociation-with-truncation-ashr.ll23 %t4 = add i16 %y, -1
24 %t5 = ashr i16 %t3, %t4
40 %t4 = add <2 x i16> %y, <i16 -1, i16 -1>
41 %t5 = ashr <2 x i16> %t3, %t4
55 %t4 = add <3 x i16> %y, <i16 -1, i16 -1, i16 -1>
56 %t5 = ashr <3 x i16> %t3, %t4
70 %t4 = add <3 x i16> %y, <i16 -1, i16 undef, i16 -1>
71 %t5 = ashr <3 x i16> %t3, %t4
85 %t4 = add <3 x i16> %y, <i16 -1, i16 undef, i16 -1>
86 %t5 = ashr <3 x i16> %t3, %t4
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dlea-dagdag.ll14 %t4 = and i8 %t1, 8
15 %t5 = zext i8 %t4 to i16
30 %t4 = and i8 %t1, 8
31 %sh = shl i8 %t4, 2
45 %t4 = and i8 %t1, 8
46 %t5 = zext i8 %t4 to i32
60 %t4 = and i8 %t1, 8
61 %sh = shl i8 %t4, 3
75 %t4 = and i16 %t1, 8
76 %t5 = zext i16 %t4 to i32
[all …]
Dsplit-store.ll14 %t4 = or i64 %t2, %t3
15 store i64 %t4, i64* %ref.tmp, align 8
29 %t4 = or i64 %t2, %t3
30 store i64 %t4, i64* %ref.tmp, align 8
45 %t4 = or i64 %t2, %t3
46 store i64 %t4, i64* %ref.tmp, align 8
61 %t4 = or i64 %t2, %t3
62 store i64 %t4, i64* %ref.tmp, align 8
75 %t4 = or i64 %t2, %t3
76 store i64 %t4, i64* %ref.tmp, align 8
[all …]
/external/llvm/test/CodeGen/MSP430/
Dbit.ll39 %t4 = zext i1 %t3 to i8
40 ret i8 %t4
49 %t4 = zext i1 %t3 to i8
50 ret i8 %t4
59 %t4 = zext i1 %t3 to i8
60 ret i8 %t4
69 %t4 = zext i1 %t3 to i8
70 ret i8 %t4
79 %t4 = icmp ne i8 %t3, 0
80 %t5 = zext i1 %t4 to i8
[all …]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Dinverses.ll10 %t4 = xor i32 %a, -1
11 %t5 = and i32 %t2, %t4
20 %t4 = xor <2 x i32> %a, <i32 -1, i32 undef>
21 %t5 = and <2 x i32> %t2, %t4
32 %t4 = xor i32 %a, -1
33 %t5 = and i32 %t2, %t4
45 %t4 = sub i32 0, %a
46 %t5 = add i32 %t2, %t4
58 %t4 = xor i32 %a, -1
59 %t5 = add i32 %t2, %t4
/external/llvm-project/llvm/test/MC/RISCV/
Drv64c-aliases-valid.s87 # CHECK-EXPAND: lui t4, 583
88 # CHECK-EXPAND: addiw t4, t4, -1875
89 # CHECK-EXPAND: c.slli t4, 14
90 # CHECK-EXPAND: addi t4, t4, -947
91 # CHECK-EXPAND: c.slli t4, 12
92 # CHECK-EXPAND: addi t4, t4, 1511
93 # CHECK-EXPAND: c.slli t4, 13
94 # CHECK-EXPAND: addi t4, t4, -272
95 li t4, 0x123456789abcdef0
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc64-P9-setb.ll14 %t4 = select i1 %t1, i64 -1, i64 %t3
15 ret i64 %t4
40 %t4 = select i1 %t1, i64 -1, i64 %t3
41 ret i64 %t4
66 %t4 = select i1 %t1, i64 -1, i64 %t3
67 ret i64 %t4
92 %t4 = select i1 %t1, i64 -1, i64 %t3
93 ret i64 %t4
118 %t4 = select i1 %t1, i64 -1, i64 %t3
119 ret i64 %t4
[all …]
/external/llvm-project/llvm/test/Transforms/NaryReassociate/
Dpr24301.ll5 define i32 @foo(i32 %t4) {
14 %t5 = add i32 %t4, 8
15 %t13 = add i32 %t4, -128 ; deleted
17 %t21 = add i32 119, %t4
24 define i32 @foo2(i32 %t4) {
34 %t5 = add i32 %t4, 8 ; initially dead
35 %t13 = add i32 %t4, -128
37 %t21 = add i32 119, %t4 ; => dead after reassociation

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