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/external/llvm/test/CodeGen/X86/
Dcrash-lre-eliminate-dead-def.ll60 %t7.0 = phi i16 [ undef, %entry ], [ %t7.1, %for.end29 ], [ %t7.19, %cleanup100 ]
94 %t7.1 = phi i16 [ %t7.2, %for.cond17 ], [ %t7.0, %if.end11 ]
100 %t7.2 = phi i16 [ %t7.3, %for.cond20 ], [ %t7.1, %for.cond15 ]
106 %t7.3 = phi i16 [ %t7.4, %for.cond23 ], [ %t7.2, %for.cond17 ]
111 %t7.4 = phi i16 [ %t7.5, %L1 ], [ %t7.3, %for.cond20 ]
116 %t7.5 = phi i16 [ %t7.19, %cleanup100 ], [ %t7.4, %for.cond23 ]
128 %t7.6 = phi i16 [ %t7.1, %for.cond32thread-pre-split ], [ %t7.17, %for.inc94 ]
150 %t7.7 = phi i16 [ %tmp5, %if.then38 ], [ %t7.15, %while.end.split ]
166 %t7.9 = phi i16 [ %t7.7, %if.end48 ], [ %.130, %for.cond52.preheader ]
175 %t7.10 = phi i16 [ %t7.19, %cleanup100.L5_crit_edge ], [ %t7.9, %if.then63 ], [ %t7.0, %if.end11 ]
[all …]
Dmasked-iv-unsafe.ll26 %t7 = load double, double* %t6
27 %t8 = fmul double %t7, 4.5
54 %t7 = load double, double* %t6
55 %t8 = fmul double %t7, 4.5
84 %t7 = load double, double* %t6
85 %t8 = fmul double %t7, 4.5
114 %t7 = load double, double* %t6
115 %t8 = fmul double %t7, 4.5
142 %t7 = load double, double* %t6
143 %t8 = fmul double %t7, 4.5
[all …]
Dmasked-iv-safe.ll28 %t7 = load double, double* %t6
29 %t8 = fmul double %t7, 4.5
61 %t7 = load double, double* %t6
62 %t8 = fmul double %t7, 4.5
96 %t7 = load double, double* %t6
97 %t8 = fmul double %t7, 4.5
131 %t7 = load double, double* %t6
132 %t8 = fmul double %t7, 4.5
164 %t7 = load double, double* %t6
165 %t8 = fmul double %t7, 4.5
[all …]
Dvec_ins_extract-1.ll8 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
29 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
34 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
58 %t9 = extractelement <4 x i32> %t13, i32 %t7
62 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
81 %t9 = extractelement <4 x i32> %t8, i32 %t7
86 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
108 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
/external/llvm-project/llvm/test/CodeGen/X86/
Dcrash-lre-eliminate-dead-def.ll60 %t7.0 = phi i16 [ undef, %entry ], [ %t7.1, %for.end29 ], [ %t7.19, %cleanup100 ]
94 %t7.1 = phi i16 [ %t7.2, %for.cond17 ], [ %t7.0, %if.end11 ]
100 %t7.2 = phi i16 [ %t7.3, %for.cond20 ], [ %t7.1, %for.cond15 ]
106 %t7.3 = phi i16 [ %t7.4, %for.cond23 ], [ %t7.2, %for.cond17 ]
111 %t7.4 = phi i16 [ %t7.5, %L1 ], [ %t7.3, %for.cond20 ]
116 %t7.5 = phi i16 [ %t7.19, %cleanup100 ], [ %t7.4, %for.cond23 ]
128 %t7.6 = phi i16 [ %t7.1, %for.cond32thread-pre-split ], [ %t7.17, %for.inc94 ]
150 %t7.7 = phi i16 [ %tmp5, %if.then38 ], [ %t7.15, %while.end.split ]
166 %t7.9 = phi i16 [ %t7.7, %if.end48 ], [ %.130, %for.cond52.preheader ]
175 %t7.10 = phi i16 [ %t7.19, %cleanup100.L5_crit_edge ], [ %t7.9, %if.then63 ], [ %t7.0, %if.end11 ]
[all …]
Dvec_ins_extract-1.ll8 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
31 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
36 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
62 %t9 = extractelement <4 x i32> %t13, i32 %t7
66 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
87 %t9 = extractelement <4 x i32> %t8, i32 %t7
92 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
116 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
/external/libaom/libaom/av1/common/arm/
Dwiener_convolve_neon.c81 uint8x8_t t0, t1, t2, t3, t4, t5, t6, t7; in av1_wiener_convolve_add_src_neon() local
98 load_u8_8x8(src_ptr, src_stride, &t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in av1_wiener_convolve_add_src_neon()
99 transpose_u8_8x8(&t0, &t1, &t2, &t3, &t4, &t5, &t6, &t7); in av1_wiener_convolve_add_src_neon()
115 load_u8_8x8(s, src_stride, &t7, &t8, &t9, &t10, &t11, &t12, &t13, &t14); in av1_wiener_convolve_add_src_neon()
116 transpose_u8_8x8(&t7, &t8, &t9, &t10, &t11, &t12, &t13, &t14); in av1_wiener_convolve_add_src_neon()
125 res0 = vreinterpretq_s16_u16(vaddl_u8(t1, t7)); in av1_wiener_convolve_add_src_neon()
133 res1 = vreinterpretq_s16_u16(vaddl_u8(t3, t7)); in av1_wiener_convolve_add_src_neon()
141 res2 = vreinterpretq_s16_u16(vaddl_u8(t5, t7)); in av1_wiener_convolve_add_src_neon()
149 res3 = vreinterpretq_s16_u16(vmovl_u8(t7)); in av1_wiener_convolve_add_src_neon()
155 res2 = vreinterpretq_s16_u16(vaddl_u8(t7, t9)); in av1_wiener_convolve_add_src_neon()
[all …]
/external/llvm-project/llvm/test/Assembler/
Dmulti-mod-disassemble.ll8 ; RUN: llvm-dis -o %t7.o %t6.o
9 ; RUN: diff %t7.o.0 %t7.o.1
10 ; RUN: FileCheck < %t7.o.0 %s
11 ; RUN: FileCheck < %t7.o.1 %s
Dmulti-summary-disassemble.ll8 ; RUN: llvm-dis -o %t7.o %t6.o
9 ; RUN: diff %t7.o.0 %t7.o.1
10 ; RUN: FileCheck < %t7.o.0 %s
11 ; RUN: FileCheck < %t7.o.1 %s
/external/speex/libspeexdsp/
Dsmallft.c278 int t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10; in dradfg() local
424 t7=idl1; in dradfg()
427 ch2[t4++]=c2[ik]+ar1*c2[t7++]; in dradfg()
447 t7=t2; in dradfg()
452 ch2[t7++]+=ai2*c2[t9++]; in dradfg()
502 t7=t4; in dradfg()
506 cc[t5]=ch[t7]; in dradfg()
509 t7+=ido; in dradfg()
526 t7=t3; in dradfg()
532 cc[i+t7-1]=ch[i+t8-1]+ch[i+t9-1]; in dradfg()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dmidpoint-int.ll29 %t7 = sub i32 %t6, %t5
30 %t8 = lshr i32 %t7, 1
52 %t7 = sub i32 %t6, %t5
53 %t8 = lshr i32 %t7, 1
79 %t7 = sub i32 %t6, %t5
80 %t8 = lshr i32 %t7, 1
104 %t7 = sub i32 %t6, %t5
105 %t8 = lshr i32 %t7, 1
131 %t7 = sub i32 %t6, %t5
132 %t8 = lshr i32 %t7, 1
[all …]
/external/python/cpython3/Lib/test/
Dtest_pkg.py257 t7, sub, subsub = None, None, None
258 import t7 as tas
262 self.assertFalse(t7)
263 from t7 import sub as subpar
267 self.assertFalse(t7)
269 from t7.sub import subsub as subsubsub
274 self.assertFalse(t7)
277 from t7.sub.subsub import spam as ham
279 self.assertFalse(t7)
/external/llvm-project/compiler-rt/lib/sanitizer_common/tests/
Dsanitizer_bvgraph_test.cpp269 BV t7; in ShortestPath() local
270 t7.clear(); in ShortestPath()
271 t7.setBit(7); in ShortestPath()
281 EXPECT_TRUE(g.isReachable(1, t7)); in ShortestPath()
283 EXPECT_EQ(0U, g.findPath(1, t7, path, 1)); in ShortestPath()
285 EXPECT_EQ(2U, g.findPath(1, t7, path, 2)); in ShortestPath()
286 EXPECT_EQ(2U, g.findPath(1, t7, path, 3)); in ShortestPath()
287 EXPECT_EQ(2U, g.findPath(1, t7, path, 4)); in ShortestPath()
288 EXPECT_EQ(2U, g.findPath(1, t7, path, 5)); in ShortestPath()
289 EXPECT_EQ(2U, g.findPath(1, t7, path, 6)); in ShortestPath()
[all …]
/external/compiler-rt/lib/sanitizer_common/tests/
Dsanitizer_bvgraph_test.cc270 BV t7; in ShortestPath() local
271 t7.clear(); in ShortestPath()
272 t7.setBit(7); in ShortestPath()
282 EXPECT_TRUE(g.isReachable(1, t7)); in ShortestPath()
284 EXPECT_EQ(0U, g.findPath(1, t7, path, 1)); in ShortestPath()
286 EXPECT_EQ(2U, g.findPath(1, t7, path, 2)); in ShortestPath()
287 EXPECT_EQ(2U, g.findPath(1, t7, path, 3)); in ShortestPath()
288 EXPECT_EQ(2U, g.findPath(1, t7, path, 4)); in ShortestPath()
289 EXPECT_EQ(2U, g.findPath(1, t7, path, 5)); in ShortestPath()
290 EXPECT_EQ(2U, g.findPath(1, t7, path, 6)); in ShortestPath()
[all …]
/external/python/cpython2/Lib/test/
Dtest_pkg.py250 t7, sub, subsub = None, None, None
251 import t7 as tas
255 self.assertFalse(t7)
256 from t7 import sub as subpar
260 self.assertFalse(t7)
262 from t7.sub import subsub as subsubsub
266 self.assertFalse(t7)
269 from t7.sub.subsub import spam as ham
271 self.assertFalse(t7)
/external/llvm/test/MC/Mips/
Dmips64-register-names-n32-n64.s30 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
35 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
40 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
45 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
46 # WARNING-NEXT: daddiu $t7, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0f,0x00,0x00]
49 daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00]
68 # [*] - t0-t3 are aliases of t4-t7 for compatibility with both the original
69 # ABI documentation (using t4-t7) and GNU As (using t0-t3)
/external/llvm-project/llvm/test/MC/Mips/
Dmips64-register-names-n32-n64.s31 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
36 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
41 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
46 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
47 # WARNING-NEXT: daddiu $t7, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0f,0x00,0x00]
50 daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00]
69 # [*] - t0-t3 are aliases of t4-t7 for compatibility with both the original
70 # ABI documentation (using t4-t7) and GNU As (using t0-t3)
/external/llvm-project/llvm/test/Transforms/LICM/
Dloopsink.ll36 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
63 %t7 = add nuw nsw i32 %iv, 1
64 %c7 = icmp eq i32 %t7, %p7
103 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
130 %t7 = add nuw nsw i32 %iv, 1
131 %c7 = icmp eq i32 %t7, %p7
165 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
192 %t7 = add nuw nsw i32 %iv, 1
193 %c7 = icmp eq i32 %t7, %p7
250 %iv = phi i32 [ %t7, %.b7 ], [ 0, %.preheader ]
[all …]
/external/ruy/ruy/
Dpack_avx2_fma.cc157 __m256i t0, t1, t2, t3, t4, t5, t6, t7;
168 t7 = _mm256_loadu_si256(reinterpret_cast<const __m256i*>(src_ptr7));
175 r5 = _mm256_unpacklo_epi32(t6, t7);
177 r7 = _mm256_unpackhi_epi32(t6, t7);
186 t7 = _mm256_unpackhi_epi64(r6, r7);
198 r6 = _mm256_permute2x128_si256(t3, t7, 0x20);
200 r7 = _mm256_permute2x128_si256(t3, t7, 0x31);
289 __m256i t0, t1, t2, t3, t4, t5, t6, t7;
300 t7 = _mm256_loadu_si256(reinterpret_cast<const __m256i*>(src_ptr7));
307 r5 = _mm256_unpacklo_epi32(t6, t7);
[all …]
Dpack_avx.cc307 __m256i t0, t1, t2, t3, t4, t5, t6, t7;
318 t7 = _mm256_loadu_si256(reinterpret_cast<const __m256i*>(src_ptr7));
325 r5 = mm256_unpacklo_epi32(t6, t7);
327 r7 = mm256_unpackhi_epi32(t6, t7);
336 t7 = mm256_unpackhi_epi64(r6, r7);
348 r6 = mm256_permute2x128_si256(t3, t7, 0x20);
350 r7 = mm256_permute2x128_si256(t3, t7, 0x31);
431 __m256i t0, t1, t2, t3, t4, t5, t6, t7;
442 t7 = _mm256_loadu_si256(reinterpret_cast<const __m256i*>(src_ptr7));
449 r5 = mm256_unpacklo_epi32(t6, t7);
[all …]
/external/llvm-project/lldb/test/API/functionalities/data-formatter/data-formatter-objc/cmtime/
Dmain.m15 CMTime t7 = CMTimeMake(10, 1);
16 t7.flags = kCMTimeFlags_Indefinite;
24 CMTimeShow(t7);
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dand-xor-merge.ll13 %t7 = xor i32 %t3, %t6
14 ret i32 %t7
25 %t7 = xor i32 %t3, %t6
26 ret i32 %t7
/external/llvm-project/clang/test/SemaCUDA/
Dasm_delayed_diags.cu67 static __device__ __host__ void t7(__m256i *p) { in t7() function
81 t7(0); in m()
96 t7(0); in main()
/external/mesa3d/src/freedreno/.gitlab-ci/reference/
DdEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log6 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
13 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
192 t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords)
229 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
236 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
240 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
275 t7 opcode: CP_BLIT (2c) (2 dwords)
371 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
375 t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
377 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
[all …]
/external/openssh/regress/
DMakefile5 REGRESS_TARGETS= t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
129 t2.out t3.out t6.out1 t6.out2 t7.out t7.out.pub \
170 $(OBJ)/t7.out:
173 t7: $(OBJ)/t7.out target
174 ${TEST_SSH_SSHKEYGEN} -lf $(OBJ)/t7.out > /dev/null
175 ${TEST_SSH_SSHKEYGEN} -Bf $(OBJ)/t7.out > /dev/null

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