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Searched refs:target_masks (Results 1 – 9 of 9) sorted by relevance

/external/arm-trusted-firmware/drivers/arm/gic/v2/
Dgicv2_main.c298 assert(driver_data->target_masks != NULL); in gicv2_set_pe_target_mask()
303 if (driver_data->target_masks[proc_num] != 0U) in gicv2_set_pe_target_mask()
310 if (driver_data->target_masks[proc_num] == 0U) { in gicv2_set_pe_target_mask()
311 driver_data->target_masks[proc_num] = in gicv2_set_pe_target_mask()
322 &driver_data->target_masks[proc_num], in gicv2_set_pe_target_mask()
323 sizeof(driver_data->target_masks[proc_num])); in gicv2_set_pe_target_mask()
433 assert(driver_data->target_masks != NULL); in gicv2_raise_sgi()
437 target = driver_data->target_masks[proc_num]; in gicv2_raise_sgi()
469 assert(driver_data->target_masks != NULL); in gicv2_set_spi_routing()
479 target = driver_data->target_masks[proc_num]; in gicv2_set_spi_routing()
/external/arm-trusted-firmware/plat/hisilicon/poplar/
Dpoplar_gicv2.c28 .target_masks = target_mask_array,
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_gicv2.c39 tegra_gic_data.target_masks = tegra_target_masks; in tegra_gic_setup()
/external/arm-trusted-firmware/plat/arm/common/
Darm_gicv2.c39 .target_masks = target_mask_array,
/external/arm-trusted-firmware/plat/marvell/armada/common/
Dmarvell_gicv2.c62 .target_masks = target_mask_array,
/external/arm-trusted-firmware/plat/qemu/common/sp_min/
Dsp_min_setup.c66 .target_masks = target_mask_array,
/external/arm-trusted-firmware/include/drivers/arm/
Dgicv2.h153 unsigned int *target_masks; member
/external/arm-trusted-firmware/plat/intel/soc/agilex/
Dbl31_plat_setup.c95 .target_masks = target_mask_array,
/external/arm-trusted-firmware/plat/intel/soc/stratix10/
Dbl31_plat_setup.c103 .target_masks = target_mask_array,